Issued Patents All Time
Showing 451–471 of 471 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5300813 | Refractory metal capped low resistivity metal conductor lines and vias | Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal | 1994-04-05 |
| 5283456 | Vertical gate transistor with low temperature epitaxial channel | Chang-Ming Hsieh, Seiki Ogura | 1994-02-01 |
| 5276338 | Bonded wafer structure having a buried insulation layer | Klaus D. Beyer, Chang-Ming Hsieh, Tsorng-Dih Yuan | 1994-01-04 |
| 5270234 | Deep submicron transistor fabrication method | Daniel Huang, Wen-Yuan Wang | 1993-12-14 |
| 5266504 | Low temperature emitter process for high performance bipolar devices | Jeffrey L. Blouse, Jack O. Chu, Brian T. Cunningham, Jeffrey P. Gambino, David E. Kotecki +2 more | 1993-11-30 |
| 5260233 | Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding | Taqi Nasser Buti, Rajiv V. Joshi, Joseph F. Shepard, Jr. | 1993-11-09 |
| 5258640 | Gate controlled Schottky barrier diode | Chang-Ming Hsieh, Phung T. Nguyen, Lawrence F. Wagner, Jr. | 1993-11-02 |
| 5258318 | Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon | Taqi Nasser Buti, Mark E. Jost, Seiki Ogura, Ronald N. Schulz | 1993-11-02 |
| 5245206 | Capacitors with roughened single crystal plates | Jack O. Chu, Toshio Mii, Joseph F. Shepard, Jr., Scott R. Stiffler, Manu J. Tejwani +1 more | 1993-09-14 |
| 5241203 | Inverse T-gate FET transistor with lightly doped source and drain region | Seiki Ogura, Joseph F. Shepard, Jr., Paul J. Tsang | 1993-08-31 |
| 5235206 | Vertical bipolar transistor with recessed epitaxially grown intrinsic base region | Brian H. Desilets, Chang-Ming Hsieh | 1993-08-10 |
| 5234535 | Method of producing a thin silicon-on-insulator layer | Klaus D. Beyer, Victor J. Silvestri, Andrie S. Yapsir | 1993-08-10 |
| 5202272 | Field effect transistor formed with deep-submicron gate | Chang-Ming Hsieh, Shantha Kumar, Zu-Jean Tien | 1993-04-13 |
| 5192708 | Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization | Klaus D. Beyer, Edward C. Fredericks, David E. Kotecki, Christopher C. Parks | 1993-03-09 |
| 5154514 | On-chip temperature sensor utilizing a Schottky barrier diode structure | Jeffrey P. Gambino, Michael Lee, Krishna Seshan, Alvin Sugerman, Francis E. Turene | 1992-10-13 |
| 5137840 | Vertical bipolar transistor with recessed epitaxially grown intrinsic base region | Brian H. Desilets, Chang-Ming Hsieh | 1992-08-11 |
| 5120668 | Method of forming an inverse T-gate FET transistor | Seiki Ogura, Joseph F. Shepard, Jr., Paul J. Tsang | 1992-06-09 |
| 5098856 | Air-filled isolation trench with chemically vapor deposited silicon dioxide cap | Klaus D. Beyer, Subodh K. Kulkarni | 1992-03-24 |
| 5043786 | Lateral transistor and method of making same | Brian H. Desilets, Chang-Ming Hsieh | 1991-08-27 |
| 4965217 | Method of making a lateral transistor | Brian H. Desilets, Chang-Ming Hsieh | 1990-10-23 |
| 4758531 | Method of making defect free silicon islands using SEG | Klaus D. Beyer, Dominic J. Schepis, Victor J. Silvestri | 1988-07-19 |