Issued Patents All Time
Showing 101–125 of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8174841 | Adaptive interconnect structure | Matthew R. Wordeman, Albert M. Young | 2012-05-08 |
| 8159028 | Metal high dielectric constant transistor with reverse-T gate | Isaac Lauer, Jeffrey W. Sleight | 2012-04-17 |
| 8138030 | Asymmetric finFET device with improved parasitic resistance and capacitance | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2012-03-20 |
| 8138052 | Metal high dielectric constant transistor with reverse-T gate | Isaac Lauer, Jeffrey W. Sleight | 2012-03-20 |
| 8110467 | Multiple Vt field-effect transistor devices | Josephine B. Chang, Renee T. Mo, Vijay Narayanan, Jeffrey W. Sleight | 2012-02-07 |
| 8080838 | Contact scheme for FINFET structures with multiple FINs | Wilfried E. Haensch, Meikei Ieong, Ghavam G. Shahidi, Huiling Shang | 2011-12-20 |
| 8059438 | Content addressable memory array programmed to perform logic operations | Gary S. Ditlow, Brian L. Ji, Robert K. Montoye | 2011-11-15 |
| 8054662 | Content addressable memory array | Gary S. Ditlow, Brian L. Ji, Robert K. Montoye | 2011-11-08 |
| 8039888 | Conductive spacers for semiconductor devices and methods of forming | Gary B. Bronner, David M. Fried, Jeffrey P. Gambino, Ramachandra Divakaruni, Haizhou Yin +2 more | 2011-10-18 |
| 8030145 | Back-gated fully depleted SOI transistor | Brian L. Ji, Arvind Kumar, Amlan Majumdar, Katherine L. Saenger, Leathen Shi +1 more | 2011-10-04 |
| 8018007 | Selective floating body SRAM cell | Josephine B. Chang, Steven J. Koester, Jeffrey W. Sleight | 2011-09-13 |
| 7985633 | Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors | Jin Cai, Josephine B. Chang, Brian L. Ji, Steven J. Koester, Amlan Majumdar | 2011-07-26 |
| 7960795 | Partially and fully silicided gate stacks | Renee T. Mo, Jeffrey W. Sleight | 2011-06-14 |
| 7948782 | Content addressable memory reference clock | Gary S. Ditlow, Brian L. Ji, Robert K. Montoye | 2011-05-24 |
| 7948307 | Dual dielectric tri-gate field effect transistor | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2011-05-24 |
| 7898894 | Static random access memory (SRAM) cells | Rajiv V. Joshi, Stephen V. Kosonocky | 2011-03-01 |
| 7893494 | Method and structure for SOI body contact FET with reduced parasitic capacitance | Anthony I. Chou, Shreesh Narasimha, Jeffrey W. Sleight | 2011-02-22 |
| 7884411 | Area-efficient gated diode structure and method of forming same | Robert H. Dennard, David M. Fried, Wing K. Luk | 2011-02-08 |
| 7855135 | Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor | Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight | 2010-12-21 |
| 7843007 | Metal high-k transistor having silicon sidewall for reduced parasitic capacitance | Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight | 2010-11-30 |
| 7839715 | SerDes double rate bitline with interlock to block precharge capture | Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino | 2010-11-23 |
| 7826251 | High performance metal gate polygate 8 transistor SRAM cell with reduced variability | Jeffrey W. Sleight | 2010-11-02 |
| 7804140 | Field effect transistor with reduced shallow trench isolation induced leakage current | Anthony I. Chou, Shreesh Narasimha, Jeffrey W. Sleight | 2010-09-28 |
| 7791110 | Integrated circuit having gates and active regions forming a regular grating | Hon-Sum Philip Wong | 2010-09-07 |
| 7785952 | Partially and fully silicided gate stacks | Renee T. Mo, Jeffrey W. Sleight | 2010-08-31 |