Issued Patents All Time
Showing 76–100 of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8563376 | Hybrid CMOS nanowire mesh device and bulk CMOS device | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-10-22 |
| 8555119 | Test structure for characterizing multi-port static random access memory and register file arrays | Jente B. Kuang, Robert K. Montoye, Hung C. Ngo, Kevin John Nowka | 2013-10-08 |
| 8551833 | Double gate planar field effect transistors | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-10-08 |
| 8541774 | Hybrid CMOS technology with nanowire devices and double gated planar devices | Sarunya Bangsaruntip, Josephine B. Chang, Jeffrey W. Sleight | 2013-09-24 |
| 8536041 | Method for fabricating transistor with high-K dielectric sidewall spacer | Isaac Lauer, Jeffrey W. Sleight | 2013-09-17 |
| 8531871 | 8-transistor SRAM cell design with Schottky diodes | Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-09-10 |
| 8526228 | 8-transistor SRAM cell design with outer pass-gate diodes | Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-09-03 |
| 8502325 | Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance | Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo | 2013-08-06 |
| 8493093 | Time division multiplexed limited switch dynamic logic | Robert K. Montoye, Yutaka Nakamura | 2013-07-23 |
| 8466012 | Bulk FinFET and SOI FinFET hybrid technology | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-06-18 |
| 8460991 | Differentially recessed contacts for multi-gate transistor of SRAM cell | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-06-11 |
| 8432723 | Nano-electro-mechanical DRAM cell | Josephine B. Chang, Michael A. Guillorn, Brian J. Li, Steven J. Koester | 2013-04-30 |
| 8426917 | Body-tied asymmetric P-type field effect transistor | Jeffrey W. Sleight, Chung-Hsun Lin, Josephine B. Chang | 2013-04-23 |
| 8397183 | Generation of asymmetric circuit devices | Jeffrey W. Sleight | 2013-03-12 |
| 8378429 | Selective floating body SRAM cell | Josephine B. Chang, Steven J. Koester, Jeffrey W. Sleight | 2013-02-19 |
| 8367485 | Embedded silicon germanium n-type filed effect transistor for reduced floating body effect | Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight | 2013-02-05 |
| 8349670 | Selective floating body SRAM cell | Josephine B. Chang, Steven J. Koester, Jeffrey W. Sleight | 2013-01-08 |
| 8338239 | High performance devices and high density devices on single chip | Isaac Lauer, Jeffrey W. Sleight | 2012-12-25 |
| 8309445 | Bi-directional self-aligned FET capacitor | Brian L. Ji, Chung-Hsun Lin, Jeffrey W. Sleight | 2012-11-13 |
| 8304837 | Differentially recessed contacts for multi-gate transistor of SRAM cell | Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight | 2012-11-06 |
| 8261138 | Test structure for characterizing multi-port static random access memory and register file arrays | Jente B. Kuang, Robert K. Montoye, Hung C. Ngo, Kevin John Nowka | 2012-09-04 |
| 8247877 | Structure with reduced fringe capacitance | Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight | 2012-08-21 |
| 8232604 | Transistor with high-k dielectric sidewall spacer | Isaac Lauer, Jeffrey W. Sleight | 2012-07-31 |
| 8216907 | Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance | Jeffrey W. Sleight, Isaac Lauer, Renee T. Mo | 2012-07-10 |
| 8193062 | Asymmetric silicon-on-insulator SRAM cell | Jeffrey W. Sleight | 2012-06-05 |