KM

Koichi Motoyama

IBM: 105 patents #518 of 70,183Top 1%
RE Renesas Electronics: 4 patents #1,016 of 4,529Top 25%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
NE Nec Electronics: 2 patents #384 of 1,789Top 25%
SS Stmicroelectronics Sa: 2 patents #601 of 1,676Top 40%
📍 Clifton Park, NY: #9 of 1,126 inventorsTop 1%
🗺 New York: #447 of 115,490 inventorsTop 1%
Overall (All Time): #11,660 of 4,157,543Top 1%
111
Patents All Time

Issued Patents All Time

Showing 51–75 of 111 patents

Patent #TitleCo-InventorsDate
11244859 Interconnects having a via-to-line spacer for preventing short circuit events between a conductive via and an adjacent line Cornelius Brown Peethala, Christopher J. Penny, Nicholas Anthony Lanzillo, Lawrence A. Clevenger 2022-02-08
11244897 Back end of line metallization Chanro Park, Kenneth Chun Kuen Cheng, Somnath Ghosh, Chih-Chao Yang 2022-02-08
11244860 Double patterning interconnect integration scheme with SAV Shyng-Tsong Chen, Terry A. Spooner, Chih-Chao Yang 2022-02-08
11244854 Dual damascene fully aligned via in interconnects Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang 2022-02-08
11244853 Fully aligned via interconnects with partially removed etch stop layer Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang 2022-02-08
11239278 Bottom conductive structure with a limited top contact area Chih-Chao Yang, Baozhen Li, Theodorus E. Standaert 2022-02-01
11239414 Physical unclonable function for MRAM structures Ruilong Xie, Alexander Reznicek, Oscar van der Straten 2022-02-01
11227792 Interconnect structures including self aligned vias Chih-Chao Yang, Terry A. Spooner, Shyng-Tsong Chen 2022-01-18
11217481 Fully aligned top vias Nicholas Anthony Lanzillo, Somnath Ghosh, Christopher J. Penny, Robert R. Robison, Lawrence A. Clevenger 2022-01-04
11205591 Top via interconnect with self-aligned barrier layer Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang 2021-12-21
11201112 Fully-aligned skip-vias Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang 2021-12-14
11201056 Pitch multiplication with high pattern fidelity Chanro Park, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2021-12-14
11183455 Interconnects with enlarged contact area Oscar van der Straten, Kenneth Chun Kuen Cheng, Joseph F. Maniscalco 2021-11-23
11177162 Trapezoidal interconnect at tight BEOL pitch Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Junli Wang, Christopher J. Penny +1 more 2021-11-16
11177163 Top via structure with enlarged contact area with upper metallization level Chanro Park, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2021-11-16
11177169 Interconnects with gouged vias Kenneth Chun Kuen Cheng, Chih-Chao Yang, Hosadurga Shobha 2021-11-16
11177170 Removal of barrier and liner layers from a bottom of a via Chanro Park, Kenneth Chun Kuen Cheng, Nicholas Anthony Lanzillo 2021-11-16
11177171 Encapsulated top via interconnects Oscar van der Straten, Kenneth Chun Kuen Cheng, Joseph F. Maniscalco 2021-11-16
11177214 Interconnects with hybrid metal conductors Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang 2021-11-16
11164774 Interconnects with spacer structure for forming air-gaps Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang 2021-11-02
11164815 Bottom barrier free interconnects without voids Kenneth Chun Kuen Cheng, Kisik Choi, Cornelius Brown Peethala, Hosadurga Shobha, Joe Lee 2021-11-02
11158538 Interconnect structures with cobalt-infused ruthenium liner and a cobalt cap Joseph F. Maniscalco, Oscar van der Straten, Scott A. DeVries, Alexander Reznicek 2021-10-26
11139201 Top via with hybrid metallization Nicholas Anthony Lanzillo, Christopher J. Penny, Somnath Ghosh, Robert R. Robison, Lawrence A. Clevenger 2021-10-05
11139202 Fully aligned top vias with replacement metal lines Chanro Park, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2021-10-05
11127676 Removal or reduction of chamfer for fully-aligned via Chanro Park, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2021-09-21