KF

Keith E. Fogel

IBM: 260 patents #100 of 70,183Top 1%
Globalfoundries: 11 patents #330 of 4,424Top 8%
KT King Abdulaziz City For Science And Technology: 8 patents #16 of 573Top 3%
EC Egypt Nanotechnology Center: 2 patents #17 of 29Top 60%
IM International Machines: 1 patents #1 of 34Top 3%
ST S.O.I. Tec Silicon On Insulator Technologies: 1 patents #92 of 155Top 60%
📍 Hopewell Junction, NY: #2 of 648 inventorsTop 1%
🗺 New York: #74 of 115,490 inventorsTop 1%
Overall (All Time): #1,636 of 4,157,543Top 1%
272
Patents All Time

Issued Patents All Time

Showing 176–200 of 272 patents

Patent #TitleCo-InventorsDate
7960263 Amorphization/templated recrystallization method for hybrid orientation substrates Katherine L. Saenger, Chun-Yung Sung, Haizhou Yin 2011-06-14
7935612 Layer transfer using boron-doped SiGe layer Stephen W. Bedell, Daniel A. Inns, Jeehwan Kim, Devendra K. Sadana, James Vichiconti 2011-05-03
7923849 Interconnections for flip-chip using lead-free solders and having reaction barrier layers Balaram Ghosal, Sung Kwon Kang, Stephen Kilpatrick, Paul A. Lauro, Henry A. Nye, III +2 more 2011-04-12
7914619 Thick epitaxial silicon by grain reorientation annealing and applications thereof Joel P. de Souza, Daniel A. Inns, Devendra K. Sadana, Katherine L. Saenger 2011-03-29
7897444 Strained semiconductor-on-insulator (sSOI) by a simox method Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Alexander Reznicek, Devendra K. Sadana +1 more 2011-03-01
7880241 Low-temperature electrically activated gate electrode and method of fabricating same John C. Arnold, Stephen W. Bedell, Devendra K. Sadana 2011-02-01
7842940 Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost Joel P. de Souza, Brian J. Greene, Devendra K. Sadana, Haining Yang 2010-11-30
7823278 Method for fabricating electrical contact buttons Gareth G. Hougham, Joanna Rosner, Paul A. Lauro, Sherif A. Goma, Joseph Zinter 2010-11-02
7816664 Defect reduction by oxidation of silicon Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Devendra K. Sadana 2010-10-19
7772096 Formation of SOI by oxidation of silicon with engineered porosity gradient Joel P. Desouza, Alexander Reznicek, Devendra K. Sadana 2010-08-10
7736152 Land grid array fabrication using elastomer core and conducting metal shell or mesh Gareth G. Hougham, Paul A. Lauro, Joseph Zinter 2010-06-15
7718231 Thin buried oxides by low-dose oxygen implantation into modified silicon Kwang Su Choe, Siegfried Maurer, Ryan Mitchell, Devendra K. Sadana 2010-05-18
7704852 Amorphization/templated recrystallization method for hybrid orientation substrates Katherine L. Saenger, Chun-Yung Sung, Haizhou Yin 2010-04-27
7691733 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics Kam-Leung Lee, Katherine L. Saenger, Chun-Yung Sung, Haizhou Yin 2010-04-06
7679141 High-quality SGOI by annealing near the alloy melting point Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Richard J. Murphy, Devendra K. Sadana 2010-03-16
7648369 Interposer with electrical contact button and method Gareth G. Hougham, Joanna Rosner, Paul A. Lauro, Sherif A. Goma, Joseph Zinter 2010-01-19
7592671 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Alexander Reznicek, Devendra K. Sadana +1 more 2009-09-22
7566482 SOI by oxidation of porous silicon Kwang Su Choe, Devendra K. Sadana 2009-07-28
7550369 Method for fabricating low-defect-density changed orientation Si Joel P. de Souza, John A. Ott, Devendra K. Sadana, Katherine L. Saenger 2009-06-23
7547616 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics Kam-Leung Lee, Katherine L. Saenger, Chun-Yung Sung, Haizhou Yin 2009-06-16
7538565 High density integrated circuit apparatus, test probe and methods of use thereof Brian S. Beaman, Paul A. Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George F. Walker 2009-05-26
7507988 Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Devendra K. Sadana 2009-03-24
7501318 Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal Stephen W. Bedell, Devendra K. Sadana, Ghavam G. Shahidi 2009-03-10
7495342 Angled flying lead wire bonding process Brian S. Beaman, Paul A. Lauro, Da-Yuan Shih 2009-02-24
7485539 Strained semiconductor-on-insulator (sSOI) by a simox method Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Alexander Reznicek, Devendra K. Sadana +1 more 2009-02-03