Issued Patents All Time
Showing 26–50 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8136066 | Apparatus and computer program product for semiconductor yield estimation | Jeanne P. Bickford, Juergen Koehl, William J. Livingstone, Daniel N. Maynard | 2012-03-13 |
| 8132129 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jeanne P. Bickford, Juergen Koehl | 2012-03-06 |
| 8042070 | Methods and system for analysis and management of parametric yield | James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Anda C. Mocuta | 2011-10-18 |
| 8010916 | Test yield estimate for semiconductor products created from a library | Jeanne P. Bickford, Markus Buehler, Juergen Koehl | 2011-08-30 |
| 7984394 | Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Juergen Koehl, Edward J. Nowak | 2011-07-19 |
| 7960836 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Juergen Koehl, Edward J. Nowak | 2011-06-14 |
| 7882463 | Integrated circuit selective scaling | Fook-Luen Heng, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Robert F. Walker | 2011-02-01 |
| 7865848 | Layout optimization using parameterized cells | Veit Gernhoefer, Michael S. Gray, Matthew T. Guzowski, Stephen L. Runyon, Robert F. Walker +1 more | 2011-01-04 |
| 7818692 | Automated optimization of device structure during circuit design stage | Dureseti Chidambarrao, Richard Q. Williams | 2010-10-19 |
| 7818694 | IC layout optimization to improve yield | Robert J. Allen, Faye D. Baker, Albert M. Chu, Michael S. Gray, Daniel N. Maynard +2 more | 2010-10-19 |
| 7761821 | Technology migration for integrated circuits with radical design restrictions | Robert J. Allen, Cam V. Endicott, Fook-Luen Heng, Kevin W. McCullen, Rani Narayan +2 more | 2010-07-20 |
| 7752580 | Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique | Sarah C. Braasch, Rouwaida N. Kanj, Daniel N. Maynard, Sani R. Nassif, Evanthia Papadopoulou | 2010-07-06 |
| 7752589 | Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design | Robert J. Allen, Sarah C. Braasch, Matthew T. Guzowski, Daniel N. Maynard, Kevin W. McCullen +3 more | 2010-07-06 |
| 7735042 | Context aware sub-circuit layout modification | Michael S. Gray, Matthew T. Guzowski, Kevin W. McCullen, Robert F. Walker, Xin Yuan | 2010-06-08 |
| 7725864 | Systematic yield in semiconductor manufacture | Paul H. Bergeron, Gustavo E. Tellez | 2010-05-25 |
| 7721240 | Systematic yield in semiconductor manufacture | Paul H. Bergeron, Gustavo E. Tellez | 2010-05-18 |
| 7669170 | Circuit layout methodology using via shape process | John M. Cohn, Anthony K. Stamper, Jed H. Rankin | 2010-02-23 |
| 7661081 | Content based yield prediction of VLSI designs | Robert J. Allen, Daria R. Dooling, Daniel N. Maynard, Sarah C. Prue, Ralph J. Williams | 2010-02-09 |
| 7657859 | Method for IC wiring yield optimization, including wire widening during and after routing | John M. Cohn, Gustavo E. Tellez | 2010-02-02 |
| 7610565 | Technology migration for integrated circuits with radical design restrictions | Robert J. Allen, Cam V. Endicott, Fook-Luen Heng, Kevin W. McCullen, Rani Narayan +2 more | 2009-10-27 |
| 7568173 | Independent migration of hierarchical designs with methods of finding and fixing opens during migration | Veit Gernhoefer, Matthew T. Guzowski, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon +5 more | 2009-07-28 |
| 7503020 | IC layout optimization to improve yield | Robert J. Allen, Faye D. Baker, Albert M. Chu, Michael S. Gray, Daniel N. Maynard +2 more | 2009-03-10 |
| 7496874 | Semiconductor yield estimation | Jeanne P. Bickford, Juergen Koehl, William J. Livingstone, Daniel Nelson Mayuard | 2009-02-24 |
| 7490308 | Method for implementing overlay-based modification of VLSI design layout | Christopher Gonzalez, Michael S. Gray, Matthew T. Guzowski, Stephen I. Runyon, Xiaoyun K. Wu | 2009-02-10 |
| 7487476 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jeanne P. Bickford, Juergen Koehl | 2009-02-03 |