Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7484197 | Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs | Robert J. Allen, Michael S. Gray, Fook-Luen Heng, Kevin W. McCullen, Rani Narayan +2 more | 2009-01-27 |
| 7454721 | Method, apparatus and computer program product for optimizing an integrated circuit layout | Rani Narayan, Robert F. Walker | 2008-11-18 |
| 7398485 | Yield optimization in router for systematic defects | Jeanne P. Bickford, Markus Buehler, Juergen Koehl, Daniel N. Maynard | 2008-07-08 |
| 7389480 | Content based yield prediction of VLSI designs | Robert J. Allen, Daria R. Dooling, Daniel N. Maynard, Sarah C. Prue, Ralph J. Williams | 2008-06-17 |
| 7386815 | Test yield estimate for semiconductor products created from a library | Jeanne P. Bickford, Markus Buehler, Juergen Koehl | 2008-06-10 |
| 7363601 | Integrated circuit selective scaling | Fook-Luen Heng, Kevin W. McCullen, Rani Narayan, Stephen L. Runyon, Robert F. Walker | 2008-04-22 |
| 7337415 | Systematic yield in semiconductor manufacture | Paul H. Bergeron, Gustavo E. Tellez | 2008-02-26 |
| 7308669 | Use of redundant routes to increase the yield and reliability of a VLSI layout | Markus Buehler, John M. Cohn, David J. Hathaway, Juergen Koehl | 2007-12-11 |
| 7302651 | Technology migration for integrated circuits with radical design restrictions | Robert J. Allen, Cam V. Endicott, Fook-Luen Heng, Kevin W. McCullen, Rani Narayan +2 more | 2007-11-27 |
| 7290226 | Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic | Anthony Correale, Jr., Lewis W. Dewey, III | 2007-10-30 |
| 7260790 | Integrated circuit yield enhancement using Voronoi diagrams | Robert J. Allen, Michael S. Gray, Mervyn Y. Tan, Robert F. Walker | 2007-08-21 |
| 7257783 | Technology migration for integrated circuits with radical design restrictions | Robert J. Allen, Cam V. Endicott, Fook-Luen Heng, Kevin W. McCullen, Rani Narayan +2 more | 2007-08-14 |
| 7188322 | Circuit layout methodology using a shape processing application | John M. Cohn, Anthony K. Stamper, Jed H. Rankin | 2007-03-06 |
| 7120887 | Cloned and original circuit shape merging | Henry A. Bonges, III, Michael S. Gray, Kevin W. McCullen, Robert F. Walker | 2006-10-10 |
| 7093234 | Dynamic CPU usage profiling and function call tracing | Jhy-Chun Wang | 2006-08-15 |
| 7062729 | Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization | Michael S. Gray, Gustavo E. Tellez, Robert F. Walker | 2006-06-13 |
| 6970809 | Automated configuration of on-circuit facilities | Cheng A. Feng, Theodore G. Hoover, Jr., Judith K. Ingles, Jhy-Chun Wang | 2005-11-29 |
| 6941528 | Use of a layout-optimization tool to increase the yield and reliability of VLSI designs | Robert J. Allen, Gustavo E. Tellez | 2005-09-06 |