CP

Chanro Park

IBM: 163 patents #249 of 70,183Top 1%
Globalfoundries: 130 patents #9 of 4,424Top 1%
Infineon Technologies Ag: 7 patents #1,246 of 7,486Top 20%
GU Globalfoundries U.S.: 5 patents #117 of 665Top 20%
SE Sematech: 2 patents #22 of 123Top 20%
AS Adeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
AS Altis Semiconductor, Snc: 1 patents #12 of 27Top 45%
TE Tessera: 1 patents #207 of 271Top 80%
AS Altis Semiconductor: 1 patents #7 of 35Top 20%
📍 Clifton Park, NY: #3 of 1,126 inventorsTop 1%
🗺 New York: #58 of 115,490 inventorsTop 1%
Overall (All Time): #1,247 of 4,157,543Top 1%
304
Patents All Time

Issued Patents All Time

Showing 76–100 of 304 patents

Patent #TitleCo-InventorsDate
11569361 Nanosheet transistors with wrap around contact Julien Frougier, Ruilong Xie, Kangguo Cheng 2023-01-31
11527535 Variable sheet forkFET device Julien Frougier, Ruilong Xie, Kangguo Cheng 2022-12-13
11476163 Confined gate recessing for vertical transport field effect transistors Ruilong Xie, Sung-Dae Suk, Heng Wu 2022-10-18
11456181 Cross-bar fin formation Kangguo Cheng, Ruilong Xie, Juntao Li 2022-09-27
11443982 Formation of trench silicide source or drain contacts without gate damage Andrew M. Greene, Ruilong Xie, Laertis Economikos, Veeraraghavan S. Basker, Hui Zang 2022-09-13
11437489 Techniques for forming replacement metal gate for VFET Ruilong Xie, Heng Wu, Kangguo Cheng 2022-09-06
11410879 Subtractive back-end-of-line vias Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2022-08-09
11380581 Interconnect structures of semiconductor devices having a via structure through an upper conductive line Andre P. Labonte, Catherine B. Labelle 2022-07-05
11328954 Bi metal subtractive etch for trench and via formation Yann Mignot, Chih-Chao Yang, Injo Ok, Hsueh-Chung Chen 2022-05-10
11315872 Self-aligned top via Koichi Motoyama, Kenneth Chun Kuen Cheng, Kisik Choi, Chih-Chao Yang 2022-04-26
11315799 Back end of line structures with metal lines with alternating patterning and metallization schemes Ruilong Xie, Chih-Chao Yang, Kangguo Cheng, Juntao Li 2022-04-26
11309220 Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor Ruilong Xie, Min Gyu Sung 2022-04-19
11289375 Fully aligned interconnects with selective area deposition Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang 2022-03-29
11282838 Stacked gate structures Chen Zhang, Dechao Guo, Junli Wang, Ruilong Xie, Kangguo Cheng +5 more 2022-03-22
11270913 BEOL metallization formation Kenneth Chun Kuen Cheng, Koichi Motoyama, Brent A. Anderson, Somnath Ghosh 2022-03-08
11264481 Self-aligned source and drain contacts Kangguo Cheng, Ruilong Xie, Juntao Li 2022-03-01
11257718 Contact structures Stan Tsai 2022-02-22
11244854 Dual damascene fully aligned via in interconnects Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang 2022-02-08
11244853 Fully aligned via interconnects with partially removed etch stop layer Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2022-02-08
11244897 Back end of line metallization Koichi Motoyama, Kenneth Chun Kuen Cheng, Somnath Ghosh, Chih-Chao Yang 2022-02-08
11211462 Using selectively formed cap layers to form self-aligned contacts to source/drain regions Choonghyun Lee, Kangguo Cheng, Ruilong Xie 2021-12-28
11211452 Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts Ruilong Xie, Reinaldo Vega, Kangguo Cheng, Juntao Li 2021-12-28
11205591 Top via interconnect with self-aligned barrier layer Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang 2021-12-21
11201056 Pitch multiplication with high pattern fidelity Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang 2021-12-14
11201112 Fully-aligned skip-vias Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang 2021-12-14