Issued Patents All Time
Showing 201–225 of 757 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9659931 | Fin cut on sit level | Kangguo Cheng, Alexander Reznicek, Tenko Yamashita | 2017-05-23 |
| 9653541 | Structure and method to make strained FinFET with improved junction capacitance and low leakage | Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2017-05-16 |
| 9653285 | Double aspect ratio trapping | Kangguo Cheng, Bruce B. Doris, Alexander Reznicek | 2017-05-16 |
| 9647113 | Strained FinFET by epitaxial stressor independent of gate pitch | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek, Charan V. Surisetty | 2017-05-09 |
| 9634027 | CMOS structure on SSOI wafer | Bruce B. Doris, Hong He, Junli Wang | 2017-04-25 |
| 9634004 | Forming reliable contacts on tight semiconductor pitch | Xiuyu Cai, Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2017-04-25 |
| 9633943 | Method and structure for forming on-chip anti-fuse with reduced breakdown voltage | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-04-25 |
| 9633911 | Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs | Kangguo Cheng, Bruce B. Doris, Qing Liu, Nicolas Loubet, Scott Luning | 2017-04-25 |
| 9633908 | Method for forming a semiconductor structure containing high mobility semiconductor channel materials | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-04-25 |
| 9633906 | Gate structure cut after formation of epitaxial active regions | Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Theodorus E. Standaert, Ruilong Xie | 2017-04-25 |
| 9627491 | Aspect ratio trapping and lattice engineering for III/V semiconductors | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-04-18 |
| 9627377 | Self-aligned dielectric isolation for FinFET devices | Marc A. Bergendahl, Kangguo Cheng, David V. Horak, Shom Ponoth, Theodorus E. Standaert +4 more | 2017-04-18 |
| 9627278 | Method of source/drain height control in dual epi finFET formation | Veeraraghavan S. Basker, Kangguo Cheng | 2017-04-18 |
| 9627270 | Dual work function integration for stacked FinFET | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-04-18 |
| 9620641 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Kangguo Cheng, Ramachandra Divakaruni, Alexander Reznicek, Soon-Cheon Seo | 2017-04-11 |
| 9613954 | Selective removal of semiconductor fins | Veeraraghavan S. Basker, Kangguo Cheng | 2017-04-04 |
| 9608063 | Nanowire transistor structures with merged source/drain regions using auxiliary pillars | Pouya Hashemi, Alexander Reznicek | 2017-03-28 |
| 9607990 | Method to form strained nFET and strained pFET nanowires on a same substrate | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-03-28 |
| 9607898 | Simultaneously fabricating a high voltage transistor and a finFET | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2017-03-28 |
| 9601511 | Low leakage dual STI integrated circuit including FDSOI transistors | Maud Vinet, Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Yannick Le Tiec +1 more | 2017-03-21 |
| 9601345 | Fin trimming in a double sit process | Kangguo Cheng, Matthew E. Colburn, Bruce B. Doris | 2017-03-21 |
| 9595595 | Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-03-14 |
| 9595525 | Semiconductor device including nanowire transistors with hybrid channels | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-03-14 |
| 9590077 | Local SOI fins with multiple heights | Kangguo Cheng, Joel P. de Souza, Alexander Reznicek, Dominic J. Schepis | 2017-03-07 |
| 9590037 | p-FET with strained silicon-germanium channel | Kangguo Cheng, Alexander Reznicek, Ghavam G. Shahidi | 2017-03-07 |