Issued Patents All Time
Showing 176–200 of 757 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9735160 | Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-08-15 |
| 9728625 | Fin formation in fin field effect transistors | Kangguo Cheng, Bruce B. Doris, Hong He, Yunpeng Yin | 2017-08-08 |
| 9728649 | Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication | Thomas N. Adam, Kangguo Cheng, Alexander Reznicek, Raghavasimhan Sreenivasan | 2017-08-08 |
| 9721851 | Silicon-germanium fin formation | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-08-01 |
| 9721885 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Kangguo Cheng, Juntao Li | 2017-08-01 |
| 9716201 | Silicon heterojunction photovoltaic device with wide band gap emitter | Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi | 2017-07-25 |
| 9716064 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Kangguo Cheng, Juntao Li | 2017-07-25 |
| 9704993 | Method of preventing epitaxy creeping under the spacer | Veeraraghavan S. Basker, Kangguo Cheng, Sreenivasan Raghavasimhan | 2017-07-11 |
| 9698046 | Fabrication of III-V-on-insulator platforms for semiconductor devices | Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi | 2017-07-04 |
| 9691900 | Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch | Kangguo Cheng, Richard S. Wise | 2017-06-27 |
| 9685434 | Inter-level dielectric layer in replacement metal gates and resistor fabrication | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2017-06-20 |
| 9680015 | Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch | Kangguo Cheng, Richard S. Wise | 2017-06-13 |
| 9680045 | III-V solar cell structure with multi-layer back surface field | Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi | 2017-06-13 |
| 9673083 | Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material | Ajey Poovannummoottil Jacob, Bruce B. Doris, Kangguo Cheng, Kern Rim | 2017-06-06 |
| 9673196 | Field effect transistors with varying threshold voltages | Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Alexander Reznicek | 2017-06-06 |
| 9673296 | Semiconductor structure having a source and a drain with reverse facets | Thomas N. Adam, Kangguo Cheng, Jinghong Li, Alexander Reznicek | 2017-06-06 |
| 9673190 | ESD device compatible with bulk bias capability | Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Pranita Kerber, Balasubramanian Pranatharthiharan +1 more | 2017-06-06 |
| 9666615 | Semiconductor on insulator substrate with back bias | Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi | 2017-05-30 |
| 9666493 | Semiconductor device structure with 110-PFET and 111-NFET curent flow direction | Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek | 2017-05-30 |
| 9666267 | Structure and method for adjusting threshold voltage of the array of transistors | Jin Cai, Kangguo Cheng, Robert H. Dennard, Tak H. Ning | 2017-05-30 |
| 9660059 | Fin replacement in a field-effect transistor | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis | 2017-05-23 |
| 9660050 | Replacement low-k spacer | Xiuyu Cai, Kangguo Cheng, Ruilong Xie | 2017-05-23 |
| 9659964 | Method and structure for preventing epi merging in embedded dynamic random access memory | Veeraraghavan S. Basker, Kangguo Cheng | 2017-05-23 |
| 9659963 | Contact formation to 3D monolithic stacked FinFETs | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-05-23 |
| 9659942 | Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET) | Veeraraghavan S. Basker, Kangguo Cheng | 2017-05-23 |