Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11158633 | Multi-level isolation structure | Haiting Wang, Shesh Mani Pandey, Lixia Lei, Gregory Costrini | 2021-10-26 |
| 11133417 | Transistors with a sectioned epitaxial semiconductor layer | Judson R. Holt, Halting Wang | 2021-09-28 |
| 11127834 | Gate structures | Jiehui Shu, Halting Wang | 2021-09-21 |
| 11114466 | IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products | Jiehui Shu, Haiting Wang | 2021-09-07 |
| 11075298 | LDMOS integrated circuit product | Jiehui Shu, Judson R. Holt, Halting Wang | 2021-07-27 |
| 11075268 | Transistors with separately-formed source and drain | Jiehui Shu, Baofu Zhu, Haiting Wang | 2021-07-27 |
| 11043566 | Semiconductor structures in a wide gate pitch region of semiconductor devices | Jiehui Shu, Judson R. Holt, Haiting Wang | 2021-06-22 |
| 11004748 | Semiconductor devices with wide gate-to-gate spacing | Jiehui Shu, Haiting Wang | 2021-05-11 |
| 10937685 | Diffusion break structures in semiconductor devices | Haiting Wang, Jiehui Shu | 2021-03-02 |
| 10833067 | Metal resistor structure in at least one cavity in dielectric over TS contact and gate structure | Haiting Wang, Jiehui Shu, Scott Beasor, Zhenyu Hu | 2020-11-10 |
| 10832839 | Metal resistors with a non-planar configuration | Scott Beasor, Haiting Wang, Jiehui Shu | 2020-11-10 |
| 10825811 | Gate cut first isolation formation with contact forming process mask protection | Xiaoming Yang, Jeffrey Chee, Keith H. Tabakman | 2020-11-03 |
| 10818557 | Integrated circuit structure to reduce soft-fail incidence and method of forming same | Akshey Sehgal, Xinyuan Dou, Sunil Kumar Singh, Ravi Prakash Srivastava, Haiting Wang +1 more | 2020-10-27 |
| 10714380 | Method of forming smooth sidewall structures using spacer materials | Ravi Prakash Srivastava, Sunil Kumar Singh, Xinyuan Dou, Akshey Sehgal, Zhiguo Sun | 2020-07-14 |
| 10580857 | Method to form high performance fin profile for 12LP and above | Yanzhen Wang, Xinyuan Dou, Hongliang Shen | 2020-03-03 |
| 10446483 | Metal-insulator-metal capacitors with enlarged contact areas | Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee | 2019-10-15 |
| 10347528 | Interconnect formation process using wire trench etch prior to via etch, and related interconnect | Sunil Kumar Singh, Ravi Prakash Srivastava, Akshey Sehgal | 2019-07-09 |
| 10347531 | Middle of the line (MOL) contact formation method and structure | Xusheng Wu, Xinyuan Dou, Xiaobo Chen, Guoliang Zhu, Wenhe Lin +1 more | 2019-07-09 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Xusheng Wu, Jianwei Peng, Hsien-Ching Lo | 2019-02-19 |
| 10153211 | Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage | Yanzhen Wang, Xinyuan Dou | 2018-12-11 |
| 10121711 | Planar metrology pad adjacent a set of fins of a fin field effect transistor device | Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal | 2018-11-06 |
| 10068810 | Multiple Fin heights with dielectric isolation | Xusheng Wu, Yi Qi, Jianwei Peng, Hsien-Ching Lo | 2018-09-04 |
| 10026818 | Field effect transistor structure with recessed interlayer dielectric and method | Xusheng Wu, Wenhe Lin, Jeffrey Chee | 2018-07-17 |
| 10014296 | Fin-type field effect transistors with single-diffusion breaks and method | Xinyuan Dou, Hong Yu, Yanzhen Wang | 2018-07-03 |
| 9666476 | Dimension-controlled via formation processing | Xiang Hu, Yuping Ren, Duohui Bei, Huang Liu | 2017-05-30 |