Issued Patents All Time
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10985244 | N-well resistor | Chung Foong Tan, Baofu Zhu | 2021-04-20 |
| 10950692 | Methods of forming air gaps between source/drain contacts and the resulting devices | Ruilong Xie, Vimal Kamineni, Hui Zang | 2021-03-16 |
| 10923469 | Vertical resistor adjacent inactive gate over trench isolation | Hui Zang, Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen +2 more | 2021-02-16 |
| 10840245 | Semiconductor device with reduced parasitic capacitance | Jiehui Shu, Haiting Wang | 2020-11-17 |
| 10825910 | Shaped gate caps in dielectric-lined openings | Hui Zang | 2020-11-03 |
| 10741451 | FinFET having insulating layers between gate and source/drain contacts | Hui Zang, Laertis Economikos, Chanro Park, Ruilong Xie | 2020-08-11 |
| 10741656 | Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same | Hui Zang, Ruilong Xie, Laertis Economikos | 2020-08-11 |
| 10727133 | Method of forming gate structure with undercut region and resulting device | Qun Gao, Balaji Kannan, Haiting Wang | 2020-07-28 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven R. Soss, Lars Liebmann +1 more | 2020-06-30 |
| 10672710 | Interconnect structures with reduced capacitance | Sunil Kumar Singh | 2020-06-02 |
| 10586736 | Hybrid fin cut with improved fin profiles | Haiting Wang, Ruilong Xie, Hui Zang, Garo Derderian, Scott Beasor | 2020-03-10 |
| 10535771 | Method for forming replacement air gap | Laertis Economikos, Hui Zang, Haiting Wang, Jinping Liu | 2020-01-14 |
| 10522538 | Using source/drain contact cap during gate cut | Haiting Wang, Jiehui Shu, Laertis Economikos, Hui Zang, Ruilong Xie +2 more | 2019-12-31 |
| 10475791 | Transistor fins with different thickness gate dielectric | Hui Zang, Garo Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu | 2019-11-12 |
| 10403742 | Field-effect transistors with fins formed by a damascene-like process | Wei Zhao, Haiting Wang, David Paul Brunco, Jiehui Shu, Jinping Liu +1 more | 2019-09-03 |
| 10374029 | Semiconductor device resistor structure | Hui Zang, Josef S. Watts | 2019-08-06 |
| 10361289 | Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same | Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu +4 more | 2019-07-23 |
| 10355104 | Single-curvature cavity for semiconductor epitaxy | Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao +3 more | 2019-07-16 |
| 10347748 | Methods of forming source/drain regions on FinFET devices | Muhammad Tawhidur Rahman, Srikanth B. Samavedam | 2019-07-09 |
| 10236213 | Gate cut structure with liner spacer and related method | Jiehui Shu, Hui Zang, Laertis Economikos | 2019-03-19 |
| 10164099 | Device with diffusion blocking layer in source/drain region | Pei Zhao, Baofu Zhu, Francis Benistant | 2018-12-25 |
| 10083904 | Metholodogy for profile control and capacitance reduction | Sunil Kumar Singh | 2018-09-25 |
| 10084093 | Low resistance conductive contacts | Shiv Kumar Mishra, Sunil Kumar Singh | 2018-09-25 |
| 10079308 | Vertical transistor structure with looped channel | Hui Zang, Josef S. Watts | 2018-09-18 |
| 10062689 | Method to fabricate vertical fin field-effect-transistors | — | 2018-08-28 |