ML

Matthias Lehr

Globalfoundries: 22 patents #130 of 4,424Top 3%
AM AMD: 21 patents #507 of 9,279Top 6%
Infineon Technologies Ag: 11 patents #789 of 7,486Top 15%
SS Sap Se: 7 patents #439 of 6,322Top 7%
SA Sap Ag: 3 patents #810 of 3,812Top 25%
Merck: 3 patents #3,073 of 9,382Top 35%
UN Unknown: 1 patents #29,356 of 83,584Top 40%
VG Voith Patent Gmbh: 1 patents #277 of 717Top 40%
Overall (All Time): #30,927 of 4,157,543Top 1%
68
Patents All Time

Issued Patents All Time

Showing 26–50 of 68 patents

Patent #TitleCo-InventorsDate
8450206 Method of forming a semiconductor device including a stress buffer material formed above a low-k metallization system Axel Walter 2013-05-28
8404577 Semiconductor device having a grain orientation layer Juergen Boemmels, Ralf Richter 2013-03-26
8392573 Transport of customer flexibility changes in a multi-tenant environment Stefan Baeuerle, Karsten Fanghaenel, Bernhard Thimmel, Uwe Schlarb, Olaf Meincke +2 more 2013-03-05
8329577 Method of forming an alloy in an interconnect structure to increase electromigration resistance Moritz Andreas Meyer, Eckhard Langer 2012-12-11
8283247 Semiconductor device including a die region designed for aluminum-free solder bump connection and a test structure designed for aluminum-free wire bonding Frank Kuechenmeister, Steffi Thierbach 2012-10-09
8216880 Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protection layer Frank Kuechenmeister 2012-07-10
8114688 Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures 2012-02-14
8062982 High yield plasma etch process for interlayer dielectrics Daniel Fischer, Matthias Schaller, Kornelia Dittmar 2011-11-22
8058731 Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance Moritz Andreas Meyer, Eckhard Langer 2011-11-15
8053354 Reduced wafer warpage in semiconductors by stress engineering in the metallization system Frank Koschinsky, Joerg Hohage 2011-11-08
8043956 Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protective layer Frank Kuechenmeister 2011-10-25
8039400 Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition Frank Koschinsky, Holger Schuehrer 2011-10-18
8039958 Semiconductor device including a reduced stress configuration for metal pillars Alexander Platz, Frank Kuechenmeister 2011-10-18
7982313 Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability Michael Grillberger 2011-07-19
7867917 Etch stop layer for a metallization layer with enhanced adhesion, etch selectivity and hermeticity Joerg Hohage, Volker Kahlert 2011-01-11
7838359 Technique for forming contact insulation layers and silicide regions with different characteristics Christoph Schwan, Kai Frohberg 2010-11-23
7829889 Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures 2010-11-09
7829357 Method and test structure for monitoring CMP processes in metallization layers of semiconductor devices Michael Grillberger 2010-11-09
7713815 Semiconductor device including a vertical decoupling capacitor Kai Frohberg, Christoph Schwan 2010-05-11
7678699 Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction Joerg Hohage, Volker Kahlert 2010-03-16
7608633 Heteroaryl-substituted acetone derivatives as inhibitors of phospholipase A2 Joachim Ludwig 2009-10-27
7592258 Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same Matthias Schaller, Carsten Peters 2009-09-22
7569937 Technique for forming a copper-based contact layer without a terminal metal Frank Kuechenmeister, Gotthard Jungnickel 2009-08-04
7550396 Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device Kai Frohberg, Volker Grimm, Sven Mueller, Ralf Richter, Jochen Klais +4 more 2009-06-23
7491555 Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device Kai Frohberg, Holger Schuehrer 2009-02-17