Issued Patents All Time
Showing 26–50 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7968464 | Memory device with improved data retention | Zhida Lan, Steven C. Avanzino | 2011-06-28 |
| 7916523 | Method of erasing a resistive memory device | An-Chung Chen, Yi-Ching Wu, Swaroop Kaza | 2011-03-29 |
| 7916529 | Pin diode device and architecture | Wai Lo, Christie Marrian, Tzu-Ning Fang | 2011-03-29 |
| 7830015 | Memory device with improved data retention | Zhida Lan, Steven C. Avanzino | 2010-11-09 |
| 7706168 | Erase, programming and leakage characteristics of a resistive memory device | Tzu-Ning Fang, Steven C. Avanzino, Swaroop Kaza, Dongxiang Liao, Christie Marrian | 2010-04-27 |
| 7646624 | Method of selecting operating characteristics of a resistive memory device | Tzu-Ning Fang, Swaroop Kaza, An-Chung Chen | 2010-01-12 |
| 7468525 | Test structures for development of metal-insulator-metal (MIM) devices | Steven C. Avanzino, Suzette K. Pangrle, Manuj Rathor, An-Chung Chen, Nicholas H. Tripsas +1 more | 2008-12-23 |
| 7384800 | Method of fabricating metal-insulator-metal (MIM) device with stable data retention | Steven C. Avanzino, An-Chung Chen, Yi-Ching Wu, Suzette K. Pangrle, Jeffrey A. Shields | 2008-06-10 |
| 7289351 | Method of programming a resistive memory device | An-Chung Chen | 2007-10-30 |
| 7286388 | Resistive memory device with improved data retention | An-Chung Chen, Tzu-Ning Fang, Yi-Ching Wu, Colin S. Bill | 2007-10-23 |
| 7176113 | LDC implant for mirrorbit to improve Vt roll-off and form sharper junction | Nga-Ching Wong, Weidong Qian, Mark Randolph, Mark T. Ramsbey, Tazrien Kamal | 2007-02-13 |
| 7049188 | Lateral doped channel | Nga-Ching Wong, Timothy Thurgate | 2006-05-23 |
| 6989319 | Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices | Mark T. Ramsbey, Vei-Han Chan, Yu Sun, Chi Chang | 2006-01-24 |
| 6989320 | Bitline implant utilizing dual poly | Weidong Qian, Mark T. Ramsbey, Jean Y. Yang | 2006-01-24 |
| 6974989 | Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing | Cinti X. Chen, Boon Yong Ang, Hajime Wada, Inkuk Kang | 2005-12-13 |
| 6958272 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell | Emmanuil H. Lingunis, Nga-Ching Wong, Mark Randolph, Mark T. Ramsbey, Ashot Melik-Martirosian +2 more | 2005-10-25 |
| 6953752 | Reduced silicon gouging and common source line resistance in semiconductor devices | Yue-Song He, Zhi-Gang Wang, Richard Fastow | 2005-10-11 |
| 6934190 | Ramp source hot-hole programming for trap based non-volatile memory devices | Zengtao T. Liu, Zhizheng Liu, Yi He, Mark Randolph | 2005-08-23 |
| 6911704 | Memory cell array with staggered local inter-connect structure | Mark Randolph, Timothy Thurgate, Richard Fastow | 2005-06-28 |
| 6894932 | Dual cell memory device having a top dielectric stack | Ashot Melik-Martirosian, Mark Randolph | 2005-05-17 |
| 6894925 | Flash memory cell programming method and system | Sheunghee Park, Chi Chang, Richard Fastow, Ming Sang Kwan, Zhigang Wang | 2005-05-17 |
| 6868014 | Memory device with reduced operating voltage having dielectric stack | Ashot Melik-Martirosian, Mark Randolph | 2005-03-15 |
| 6862221 | Memory device having a thin top dielectric and method of erasing same | Ashot Melik-Martirosian, Mark Randolph | 2005-03-01 |
| 6808996 | Method for protecting gate edges from charge gain/loss in semiconductor device | Tuan Pham, Mark T. Ramsbey, Angela T. Hui, Yu Sun, Chi Chang | 2004-10-26 |
| 6795342 | System for programming a non-volatile memory cell | Yi He, Zhizheng Liu, Mark Randolph | 2004-09-21 |