Issued Patents All Time
Showing 51–75 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6795357 | Method for reading a non-volatile memory cell | Zhizheng Liu, Yi He, Mark Randolph | 2004-09-21 |
| 6768683 | Low column leakage flash memory array | Richard Fastow | 2004-07-27 |
| 6754109 | Method of programming memory cells | Richard Fastow, Zhigang Wang, Sheung-Hee Park | 2004-06-22 |
| 6737703 | Memory array with buried bit lines | Richard Fastow, Yu Sun | 2004-05-18 |
| 6735124 | Flash memory device having four-bit cells | Ashot Melik-Martirosian, Mark Randolph | 2004-05-11 |
| 6735114 | Method of improving dynamic reference tracking for flash memory unit | Darlene Hamilton, Eric M. Ajimine, Ming-Huei Shieh, Lee Cleveland, Edward Franklin Runnion +1 more | 2004-05-11 |
| 6723638 | Performance in flash memory devices | Yue-Song He, Zhi-Gang Wang | 2004-04-20 |
| 6700201 | Reduction of sector connecting line capacitance using staggered metal lines | Richard Fastow, Yue-Song He | 2004-03-02 |
| 6654283 | Flash memory array architecture and method of programming, erasing and reading thereof | — | 2003-11-25 |
| 6653189 | Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory | Yue-Song He, Timothy Thurgate, Chi Chang, Mark Randolph, Ngaching Wong | 2003-11-25 |
| 6646914 | Flash memory array architecture having staggered metal lines | Richard Fastow | 2003-11-11 |
| 6589841 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Tuan Pham, Mark T. Ramsbey, Angela T. Hui | 2003-07-08 |
| 6583009 | Innovative narrow gate formation for floating gate flash technology | Angela T. Hui, Kelwin Ko, Hiroyuki Kinoshita, Yu Sun | 2003-06-24 |
| 6548334 | Capping layer | Tuan Pham, Mark T. Ramsbey, Angela T. Hui | 2003-04-15 |
| 6524914 | Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory | Yue-Song He, Timothy Thurgate, Chi Chang | 2003-02-25 |
| 6518072 | Deposited screen oxide for reducing gate edge lifting | Carl Robert Huster, Daniel Sobek, Timothy Thurgate | 2003-02-11 |
| 6510085 | Method of channel hot electron programming for short channel NOR flash arrays | Richard Fastow, Sheunghee Park, Zhigang Wang, Chi Chang | 2003-01-21 |
| 6469939 | Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process | Zhigang Wang, Richard Fastow, Sheung-Hee Park, Chi Chang | 2002-10-22 |
| 6465835 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Tuan Pham, Mark T. Ramsbey, Angela T. Hui | 2002-10-15 |
| 6455373 | Semiconductor device having gate edges protected from charge gain/loss | Tuan Pham, Mark T. Ramsbey, Angela T. Hui, Yu Sun, Chi Chang | 2002-09-24 |
| 6456531 | Method of drain avalanche programming of a non-volatile memory cell | Janet Wang | 2002-09-24 |
| 6452840 | Feedback method to optimize electric field during channel erase of flash memory devices | Ravi Sunkavalli, Lee Cleveland, Richard Fastow, Tim Thurgate | 2002-09-17 |
| 6448608 | Capping layer | Tuan Pham, Mark T. Ramsbey, Angela T. Hui | 2002-09-10 |
| 6438037 | Threshold voltage compacting for non-volatile semiconductor memory designs | Richard Fastow, Xin Guo | 2002-08-20 |
| 6410956 | Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices | Vei-Han Chan, Scott Luning, Mark Randolph, Nicholas H. Tripsas, Daniel Sobek +2 more | 2002-06-25 |