Issued Patents All Time
Showing 76–100 of 135 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5930634 | Method of making an IGFET with a multilevel gate | Frederick N. Hause, H. Jim Fulford, Mark I. Gardner, Mark W. Michael, Bradley T. Moore +1 more | 1999-07-27 |
| 5930642 | Transistor with buried insulative layer beneath the channel region | Bradley T. Moore, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 1999-07-27 |
| 5926713 | Method for achieving global planarization by forming minimum mesas in large field areas | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Mark W. Michael, William S. Brennan | 1999-07-20 |
| 5926717 | Method of making an integrated circuit with oxidizable trench liner | Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 1999-07-20 |
| 5923982 | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps | Daniel Kadosh, Mark I. Gardner | 1999-07-13 |
| 5924008 | Integrated circuit having local interconnect for reducing signal cross coupled noise | Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 1999-07-13 |
| 5918129 | Method of channel doping using diffusion from implanted polysilicon | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-06-29 |
| 5918126 | Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-06-29 |
| 5913106 | Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques | Frederick N. Hause, Charles E. May | 1999-06-15 |
| 5907764 | In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers | John K. Lowell, Fred N. Hause | 1999-05-25 |
| 5904539 | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties | Fred N. Hause, Charles E. May, Mark I. Gardner, Kuang-Yeh Chang | 1999-05-18 |
| 5899732 | Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device | Mark I. Gardner, Derick J. Wristers, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 1999-05-04 |
| 5899727 | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Mark W. Michael, William S. Brennan | 1999-05-04 |
| 5894168 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1999-04-13 |
| 5888675 | Reticle that compensates for radiation-induced lens error in a photolithographic system | Bradley T. Moore, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 1999-03-30 |
| 5885887 | Method of making an igfet with selectively doped multilevel polysilicon gate | Frederick N. Hause, H. Jim Fulford Jr., Mark I. Gardner, Mark W. Michael, Bradley T. Moore +1 more | 1999-03-23 |
| 5885877 | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric | Mark I. Gardner, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh, Mark W. Michael +2 more | 1999-03-23 |
| 5877058 | Method of forming an insulated-gate field-effect transistor with metal spacers | Mark I. Gardner, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-03-02 |
| 5874346 | Subtrench conductor formation with large tilt angle implant | H. Jim Fulford Jr. | 1999-02-23 |
| 5866945 | Borderless vias with HSQ gap filled patterned metal layers | Robert Chen, Jeffrey A. Shields, Khanh Tran | 1999-02-02 |
| 5854515 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-12-29 |
| 5854131 | Integrated circuit having horizontally and vertically offset interconnect lines | Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford Jr., Fred N. Hause, William S. Brennan | 1998-12-29 |
| 5851913 | Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process | William S. Brennan, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-12-22 |
| 5851891 | IGFET method of forming with silicide contact on ultra-thin gate | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-12-22 |
| 5851889 | Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric | Mark W. Michael | 1998-12-22 |