Issued Patents All Time
Showing 51–75 of 135 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6057603 | Fabrication of integrated circuit inter-level dielectrics using a stop-on-metal dielectric polish process | — | 2000-05-02 |
| 6054356 | Transistor and process of making a transistor having an improved LDD masking material | Mark W. Michael, Fred N. Hause | 2000-04-25 |
| 6049134 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 2000-04-11 |
| 6048785 | Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-04-11 |
| 6044203 | Rapid thermal anneal system and method including improved temperature sensing and monitoring | Frederick N. Hause, Charles E. May | 2000-03-28 |
| 6043544 | Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric | Mark W. Michael | 2000-03-28 |
| 6043147 | Method of prevention of degradation of low dielectric constant gap-fill material | Robert Chen, Jeffrey A. Shields, Khanh Tran | 2000-03-28 |
| 6037607 | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques | Frederick N. Hause, Charles E. May | 2000-03-14 |
| 6033921 | Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface | Charles E. May | 2000-03-07 |
| 6031289 | Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines | H. Jim Fulford, Basab Bandyopadhyay, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-02-29 |
| 6030875 | Method for making semiconductor device having nitrogen-rich active region-channel interface | Charles E. May, Michael Duane | 2000-02-29 |
| 6030752 | Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-02-29 |
| 6027859 | Semiconductor substrate having extended scribe line test structure and method of fabrication thereof | Mark W. Michael, Fred N. Hause | 2000-02-22 |
| 5998293 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Mark W. Michael, William S. Brennan, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1999-12-07 |
| 5981357 | Semiconductor trench isolation with improved planarization methodology | Fred N. Hause, Charles E. May, Mark I. Gardner, Kuang-Yeh Chang | 1999-11-09 |
| 5976956 | Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device | Mark I. Gardner, Derick J. Wristers, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 1999-11-02 |
| 5976948 | Process for forming an isolation region with trench cap | Thomas Werner | 1999-11-02 |
| 5968843 | Method of planarizing a semiconductor topography using multiple polish pads | H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1999-10-19 |
| 5963803 | Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths | Mark W. Michael, Charles E. May | 1999-10-05 |
| 5963783 | In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers | John K. Lowell, Fred N. Hause | 1999-10-05 |
| 5962894 | Trench transistor with metal spacers | Mark I. Gardner, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-10-05 |
| 5953626 | Dissolvable dielectric method | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Mark W. Michael, William S. Brennan | 1999-09-14 |
| 5950106 | Method of patterning a metal substrate using spin-on glass as a hard mask | Charles E. May | 1999-09-07 |
| 5949126 | Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench | Fred N. Hause, Charles E. May | 1999-09-07 |
| 5937299 | Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls | Mark W. Michael, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 1999-08-10 |