Issued Patents All Time
Showing 26–50 of 135 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6156649 | Method of forming uniform sheet resistivity salicide | Fred N. Hause, Charles E. May | 2000-12-05 |
| 6153833 | Integrated circuit having interconnect lines separated by a dielectric having a capping layer | Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 2000-11-28 |
| 6150721 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-11-21 |
| 6146978 | Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance | Mark W. Michael, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2000-11-14 |
| 6137182 | Method of reducing via and contact dimensions beyond photolithography equipment limits | Fred N. Hause, Mark I. Gardner | 2000-10-24 |
| 6133628 | Metal layer interconnects with improved performance characteristics | — | 2000-10-17 |
| 6127264 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6127719 | Subfield conductive layer and method of manufacture | H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6114219 | Method of manufacturing an isolation region in a semiconductor device using a flowable oxide-generating material | Thomas E. Spikes, Jr., Sey-Ping Sun | 2000-09-05 |
| 6111260 | Method and apparatus for in situ anneal during ion implant | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-29 |
| 6104064 | Asymmetrical transistor structure | Daniel Kadosh, Mark I. Gardner, Michael Duane, Jon D. Cheek, Fred N. Hause +1 more | 2000-08-15 |
| 6100146 | Method of forming trench transistor with insulative spacers | Mark I. Gardner, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-08 |
| 6096639 | Method of forming a local interconnect by conductive layer patterning | Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-01 |
| 6091149 | Dissolvable dielectric method and structure | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Mark W. Michael, William S. Brennan | 2000-07-18 |
| 6090703 | Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan, Fred N. Hause, Mark W. Michael | 2000-07-18 |
| 6087706 | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls | Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2000-07-11 |
| 6087724 | HSQ with high plasma etching resistance surface for borderless vias | Jeffrey A. Shields, Khanh Tran, Robert Chen | 2000-07-11 |
| 6083851 | HSQ with high plasma etching resistance surface for borderless vias | Jeffrey A. Shields, Khanh Tran, Robert Chen | 2000-07-04 |
| 6080629 | Ion implantation into a gate electrode layer using an implant profile displacement layer | Mark I. Gardner, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-06-27 |
| 6078080 | Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region | Daniel Kadosh, Mark I. Gardner | 2000-06-20 |
| 6074904 | Method and structure for isolating semiconductor devices after transistor formation | Thomas E. Spikes, Jr., Mark W. Michael, Mark I. Gardner | 2000-06-13 |
| 6071749 | Process for forming a semiconductor device with controlled relative thicknesses of the active region and gate electrode | Charles E. May | 2000-06-06 |
| 6066885 | Subtrench conductor formed with large tilt angle implant | H. Jim Fulford | 2000-05-23 |
| 6060384 | Borderless vias with HSQ gap filled patterned metal layers | Robert Chen, Jeffrey A. Shields, Khanh Tran | 2000-05-09 |
| 6060345 | Method of making NMOS and PMOS devices with reduced masking steps | Frederick N. Hause, H. Jim Fulford, Mark I. Gardner, Mark W. Michael, Bradley T. Moore +1 more | 2000-05-09 |