Issued Patents All Time
Showing 101–125 of 135 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5850105 | Substantially planar semiconductor topography using dielectrics and chemical mechanical polish | Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 1998-12-15 |
| 5847462 | Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan, Fred N. Hause, Mark W. Michael | 1998-12-08 |
| 5846876 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-12-08 |
| 5846862 | Semiconductor device having a vertical active region and method of manufacture thereof | Charles E. May | 1998-12-08 |
| 5843625 | Method of reducing via and contact dimensions beyond photolithography equipment limits | Fred N. Hause, Mark I. Gardner | 1998-12-01 |
| 5840451 | Individually controllable radiation sources for providing an image pattern in a photolithographic system | Bradley T. Moore, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 1998-11-24 |
| 5837557 | Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-11-17 |
| 5830773 | Method for forming semiconductor field region dielectrics having globally planarized upper surfaces | William S. Brennan, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Mark W. Michael | 1998-11-03 |
| 5827776 | Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-10-27 |
| 5827761 | Method of making NMOS and devices with sequentially formed gates having different gate lengths | H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-10-27 |
| 5814555 | Interlevel dielectric with air gaps to lessen capacitive coupling | Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-09-29 |
| 5801075 | Method of forming trench transistor with metal spacers | Mark I. Gardner, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-09-01 |
| 5792706 | Interlevel dielectric with air gaps to reduce permitivity | Mark W. Michael, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-08-11 |
| 5783458 | Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer | Daniel Kadosh, Fred N. Hause | 1998-07-21 |
| 5783864 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Mark W. Michael, William S. Brennan, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1998-07-21 |
| 5783481 | Semiconductor interlevel dielectric having a polymide for producing air gaps | William S. Brennan, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-07-21 |
| 5767012 | Method of forming a recessed interconnect structure | H. Jim Fulford, Basab Bandyopadhyay, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-06-16 |
| 5766803 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-06-16 |
| 5767000 | Method of manufacturing subfield conductive layer | H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1998-06-16 |
| 5759913 | Method of formation of an air gap within a semiconductor dielectric by solvent desorption | H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1998-06-02 |
| 5759897 | Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region | Daniel Kadosh, Mark I. Gardner | 1998-06-02 |
| 5759871 | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques | Frederick N. Hause, Charles E. May | 1998-06-02 |
| 5733798 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-03-31 |
| 5723238 | Inspection of lens error associated with lens heating in a photolithographic system | Bradley T. Moore, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 1998-03-03 |
| 5717242 | Integrated circuit having local interconnect for reduing signal cross coupled noise | Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 1998-02-10 |