Issued Patents All Time
Showing 26–50 of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6958264 | Scribe lane for gettering of contaminants on SOI wafers and gettering method | — | 2005-10-25 |
| 6943087 | Semiconductor on insulator MOSFET having strained silicon channel | Qi Xiang, Jung-Suk Goo, James Pan | 2005-09-13 |
| 6924182 | Strained silicon MOSFET having reduced leakage and method of its formation | Qi Xiang, Minh Van Ngo, Eric N. Paton, Haihong Wang | 2005-08-02 |
| 6905971 | Treatment of dielectric material to enhance etch rate | Cyrus E. Tabery, Chih-Yuh Yang, William G. En, Joong S. Jeon, Minh Van Ngo | 2005-06-14 |
| 6893929 | Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends | Qi Xiang, Minh Van Ngo, Haihong Wang | 2005-05-17 |
| 6858503 | Depletion to avoid cross contamination | Minh Van Ngo, Paul R. Besser, Qi Xiang, Eric N. Paton, Jung-Suk Goo | 2005-02-22 |
| 6855989 | Damascene finfet gate with selective metal interdiffusion | Haihong Wang, Shibly S. Ahmed, Bin Yu | 2005-02-15 |
| 6855982 | Self aligned double gate transistor having a strained channel region and process therefor | Qi Xiang, James Pan | 2005-02-15 |
| 6852576 | Method for forming structures in finfet devices | Haihong Wang, Bin Yu | 2005-02-08 |
| 6842048 | Two transistor NOR device | Zoran Krivokapic, Judy Xilin An, Haihong Wang | 2005-01-11 |
| 6833587 | Heat removal in SOI devices using a buried oxide layer/conductive layer combination | — | 2004-12-21 |
| 6812119 | Narrow fins by oxidation in double-gate finfet | Shibly S. Ahmed, Haihong Wang, Bin Yu | 2004-11-02 |
| 6800910 | FinFET device incorporating strained silicon in the channel region | Jung-Suk Goo, Haihong Wang, Qi Xiang | 2004-10-05 |
| 6790782 | Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal | Chih-Yuh Yang, Cyrus E. Tabery | 2004-09-14 |
| 6787864 | Mosfets incorporating nickel germanosilicided gate and methods for their formation | Eric N. Paton, Qi Xiang, Paul R. Besser, Minh Van Ngo, Haihong Wang | 2004-09-07 |
| 6764898 | Implantation into high-K dielectric material after gate etch to facilitate removal | William G. En, Joong S. Jeon, Minh Van Ngo | 2004-07-20 |
| 6764966 | Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric | William G. En, Arvind Halliyal, Minh Van Ngo, Chih-Yuh Yang | 2004-07-20 |
| 6762448 | FinFET device with multiple fin structures | Haihong Wang, Bin Yu | 2004-07-13 |
| 6670260 | Transistor with local insulator structure | Bin Yu, Shekhar Pramanick | 2003-12-30 |
| 6619878 | Fastening means | Shyh-Jen Wang, Shyh-Yau Wang, Su-Chen Chen | 2003-09-16 |
| 6566212 | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions | Bin Yu | 2003-05-20 |
| 6534379 | Linerless shallow trench isolation method | Philip A. Fisher, Matthew S. Buynoski | 2003-03-18 |
| 6531753 | Embedded conductor for SOI devices using a buried conductive layer/conductive plug combination | — | 2003-03-11 |
| 6492249 | High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric | Qi Xiang, Matthew S. Buynoski | 2002-12-10 |
| 6486038 | Method for and device having STI using partial etch trench bottom liner | Witold P. Maszara, Qi Xiang | 2002-11-26 |