Issued Patents All Time
Showing 51–75 of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6483147 | Through wafer backside contact to improve SOI heat dissipation | — | 2002-11-19 |
| 6458639 | MOS transistor with stepped gate insulator | Judy Xilin An, Bin Yu | 2002-10-01 |
| 6437404 | Semiconductor-on-insulator transistor with recessed source and drain | Qi Xiang, Wei Long | 2002-08-20 |
| 6420770 | STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides | Qi Xiang, Wei Long | 2002-07-16 |
| 6380019 | Method of manufacturing a transistor with local insulator structure | Bin Yu, Shekhar Pramanick | 2002-04-30 |
| 6369429 | Low resistance composite contact structure utilizing a reaction barrier layer under a metal layer | Shekhar Pramanick, Qi Xiang | 2002-04-09 |
| 6362055 | Method of gate doping by ion implantation | Bin Yu | 2002-03-26 |
| 6342438 | Method of manufacturing a dual doped CMOS gate | Bin Yu | 2002-01-29 |
| 6291278 | Method of forming transistors with self aligned damascene gate contact | Qi Xiang, Matthew S. Buynoski | 2001-09-18 |
| 6281555 | Integrated circuit having isolation structures | Bin Yu | 2001-08-28 |
| 6274420 | Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides | Qi Xiang, Wei Long | 2001-08-14 |
| 6271563 | MOS transistor with high-K spacer designed for ultra-large-scale integration | Bin Yu | 2001-08-07 |
| 6271132 | Self-aligned source and drain extensions fabricated in a damascene contact and gate process | Qi Xiang, Matthew S. Buynoski | 2001-08-07 |
| 6262456 | Integrated circuit having transistors with different threshold voltages | Bin Yu | 2001-07-17 |
| 6248675 | Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant using lowered temperatures | Qi Xiang | 2001-06-19 |
| 6239452 | Self-aligned silicide gate technology for advanced deep submicron MOS device | Qi Xiang, Shekhar Pramanick | 2001-05-29 |
| 6238960 | Fast MOSFET with low-doped source/drain | Witold P. Maszara, Srinath Krishnan | 2001-05-29 |
| 6225661 | MOS transistor with stepped gate insulator | Judy Xilin An, Bin Yu | 2001-05-01 |
| 6207553 | Method of forming multiple levels of patterned metallization | Matthew S. Buynoski | 2001-03-27 |
| 6204138 | Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects | Srinath Krishnan, Witold P. Maszara | 2001-03-20 |
| 6200869 | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions | Bin Yu | 2001-03-13 |
| 6190980 | Method of tilted implant for pocket, halo and source/drain extension in ULSI dense structures | Bin Yu, Emi Ishida | 2001-02-20 |
| 6180469 | Low resistance salicide technology with reduced silicon consumption | Shekhar Pramanick, Qi Xiang | 2001-01-30 |
| 6180487 | Selective thinning of barrier oxide through masked SIMOX implant | — | 2001-01-30 |
| 6169039 | Electron bean curing of low-k dielectrics in integrated circuits | Shekhar Pramanick, David Bang | 2001-01-02 |