Issued Patents All Time
Showing 76–100 of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6165902 | Low resistance metal contact technology | Shekhar Pramanick, Qi Xiang | 2000-12-26 |
| 6159782 | Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant | Qi Xiang | 2000-12-12 |
| 6144063 | Ultra-thin oxide for semiconductors | Geoffrey Choh-Fei Yeap, Zoran Krivokapic | 2000-11-07 |
| 6140186 | Method of forming asymmetrically doped source/drain regions | Peng Fang, Donald L. Wollesen | 2000-10-31 |
| 6093594 | CMOS optimization method utilizing sacrificial sidewall spacer | Geoffrey Choh-Fei Yeap, Qi Xiang | 2000-07-25 |
| 6087231 | Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant | Qi Xiang | 2000-07-11 |
| 6083798 | Method of producing a metal oxide semiconductor device with raised source/drain | — | 2000-07-04 |
| 6084271 | Transistor with local insulator structure | Bin Yu, Shekhar Pramanick | 2000-07-04 |
| 6077773 | Damascene process for reduced feature size | — | 2000-06-20 |
| 6060364 | Fast Mosfet with low-doped source/drain | Witold P. Maszara, Srinath Krishnan | 2000-05-09 |
| 6036875 | Method for manufacturing a semiconductor device with ultra-fine line geometry | — | 2000-03-14 |
| 5972773 | High quality isolation for high density and high performance integrated circuits | Yowjuang W. Liu | 1999-10-26 |
| 5960322 | Suppression of boron segregation for shallow source and drain junctions in semiconductors | Qi Xiang, Geoffrey Choh-Fei Yeap, Srinath Krishnan | 1999-09-28 |
| 5937319 | Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching | Qi Xiang, Subash Gupta | 1999-08-10 |
| 5937315 | Self-aligned silicide gate technology for advanced submicron MOS devices | Qi Xiang, Shekhar Pramanick | 1999-08-10 |
| 5904528 | Method of forming asymmetrically doped source/drain regions | Peng Fang, Donald L. Wollesen | 1999-05-18 |
| 5893748 | Method for producing semiconductor devices with small contacts, vias, or damascene trenches | — | 1999-04-13 |
| 5866473 | Method of manufacturing a polysilicon gate having a dimension below the photolithography limitation | Qi Xiang | 1999-02-02 |
| 5863707 | Method for producing ultra-fine interconnection features | — | 1999-01-26 |
| 5795823 | Self aligned via dual damascene | Steven C. Avanzino, Subhash Gupta, Rich Klein, Scott Luning | 1998-08-18 |
| 5785236 | Advanced copper interconnect system that is compatible with existing IC wire bonding technology | Robin Cheung | 1998-07-28 |
| 5770519 | Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device | Richard K. Klein, Darrell M. Erb, Steven C. Avanzino, Robin Cheung, Scott Luning +2 more | 1998-06-23 |
| 5753967 | Damascene process for reduced feature size | — | 1998-05-19 |
| 5705430 | Dual damascene with a sacrificial via fill | Steven C. Avanzino, Subhash Gupta, Rich Klein, Scott Luning | 1998-01-06 |
| 5691238 | Subtractive dual damascene | Steven C. Avanzino, Subhash Gupta, Rich Klein, Scott Luning | 1997-11-25 |