Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6936506 | Strained-silicon devices with different silicon thicknesses | Derick J. Wristers, Qi Xiang, Bin Yu | 2005-08-30 |
| 6909146 | Bonded wafer with metal silicidation | Jack H. Linn, Robert K. Lowry, George V. Rouse | 2005-06-21 |
| 6833307 | Method for manufacturing a semiconductor component having an early halo implant | Derick J. Wristers, Chad Weintraub, Jon D. Cheek | 2004-12-21 |
| 6821853 | Differential implant oxide process | Scott Luning | 2004-11-23 |
| 6801096 | Ring oscillator with embedded scatterometry grate array | Hormuzdiar E. Nariman, Derick J. Wristers | 2004-10-05 |
| 6794256 | Method for asymmetric spacer formation | Mark B. Fuselier, Edward E. Ehrichs, S. Doug Ray, Chad Weintraub | 2004-09-21 |
| 6727136 | Formation of ultra-shallow depth source/drain extensions for MOS transistors | Derick J. Wristers, David Wu, Akif Sultan | 2004-04-27 |
| 6727534 | Electrically programmed MOS transistor source/drain series resistance | Qi Xiang, Derick J. Wristers | 2004-04-27 |
| 6720227 | Method of forming source/drain regions in a semiconductor device | Daniel Kadosh, Jon D. Cheek, Basab Bandyopadhyay | 2004-04-13 |
| 6707106 | Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer | Derick J. Wristers, Qi Xiang | 2004-03-16 |
| 6566696 | Self-aligned VT implant | Jon D. Cheek, Mark W. Michael, Derick J. Wristers | 2003-05-20 |
| 6541321 | Method of making transistors with gate insulation layers of differing thickness | Jon D. Cheek | 2003-04-01 |
| 6506642 | Removable spacer technique | Scott Luning, Jon D. Cheek, Daniel Kadosh, David E. Brown | 2003-01-14 |
| 6300205 | Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions | H. Jim Fulford, Jon D. Cheek, Derick J. Wristers | 2001-10-09 |
| 6274415 | Self-aligned Vt implant | Jon D. Cheek, Mark W. Michael, Derick J. Wristers | 2001-08-14 |
| 6245649 | Method for forming a retrograde impurity profile | Jon D. Cheek, Daniel Kadosh, Derick J. Wristers, H. Jim Fulford | 2001-06-12 |
| 6114211 | Semiconductor device with vertical halo region and methods of manufacture | H. Jim Fulford, Jon D. Cheek, Derick J. Wristers | 2000-09-05 |
| 6051510 | Method of using a hard mask to grow dielectrics with varying characteristics | H. Jim Fulford | 2000-04-18 |
| 6037224 | Method for growing dual oxide thickness using nitrided oxides for oxidation suppression | H. Jim Fulford | 2000-03-14 |
| 5976925 | Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode | Jon Cheek, Derick J. Wristers | 1999-11-02 |
| 5849627 | Bonded wafer processing with oxidative bonding | Jack H. Linn, Robert K. Lowry, George V. Rouse | 1998-12-15 |
| 5811334 | Wafer cleaning procedure useful in the manufacture of a non-volatile memory device | Basab Bandyopadhyay, Shyam Garg, Nipendra J. Patel, Thomas E. Spikes, Jr. | 1998-09-22 |
| 5728624 | Bonded wafer processing | Jack H. Linn, Robert K. Lowry, Geroge V. Rouse, William H. Speece | 1998-03-17 |
| 5569620 | Bonded wafer processing with metal silicidation | Jack H. Linn, Robert K. Lowry, George V. Rouse | 1996-10-29 |
| 5549786 | Highly selective, highly uniform plasma etch process for spin-on glass | Stephen Alister Jones, Shyam Garg, Miguel Santana, Jr. | 1996-08-27 |