WS

William H. Speece

Harris: 6 patents #258 of 2,288Top 15%
IA Intersil Americas: 3 patents #214 of 468Top 50%
Overall (All Time): #522,643 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7052973 Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone Jack H. Linn, Michael G. Shlepr, George V. Rouse 2006-05-30
6825532 Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone Jack H. Linn, Michael G. Shlepr, George V. Rouse 2004-11-30
6255195 Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method Jack H. Linn, Michael G. Shlepr, George V. Rouse 2001-07-03
5728624 Bonded wafer processing Jack H. Linn, Robert K. Lowry, Geroge V. Rouse, James F. Buller 1998-03-17
5517047 Bonded wafer processing Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller 1996-05-14
H1435 SOI CMOS device having body extension for providing sidewall channel Richard D. Cherne, Jack E. Clark, II, Glenn A. Dejong, Richard L. Lichtel, Jr., Wesley H. Morris 1995-05-02
5391903 Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits Kurt Strater, Edward F. Hand 1995-02-21
5362667 Bonded wafer processing Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller 1994-11-08
5298434 Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits Kurt Strater, Edward F. Hand 1994-03-29
5293052 SOT CMOS device having differentially doped body extension for providing improved backside leakage channel stop Richard D. Cherne, James F. Buller 1994-03-08