Issued Patents All Time
Showing 201–225 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6103559 | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication | Mark I. Gardner, Derick J. Wristers | 2000-08-15 |
| 6104063 | Multiple spacer formation/removal technique for forming a graded junction | Mark I. Gardner, Derick J. Wristers | 2000-08-15 |
| 6100146 | Method of forming trench transistor with insulative spacers | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-08 |
| 6100173 | Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process | Mark I. Gardner, Charles E. May | 2000-08-08 |
| 6097062 | Optimized trench edge formation integrated with high quality gate formation | Mark I. Gardner, Derick J. Wristers | 2000-08-01 |
| 6096643 | Method of fabricating a semiconductor device having polysilicon line with extended silicide layer | Homi E. Nariman, Charles E. May | 2000-08-01 |
| 6096639 | Method of forming a local interconnect by conductive layer patterning | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-01 |
| 6093611 | Oxide liner for high reliability with reduced encroachment of the source/drain region | Mark I. Gardner, Derick J. Wristers | 2000-07-25 |
| 6090676 | Process for making high performance MOSFET with scaled gate electrode thickness | Mark I. Gardner, Charles E. May | 2000-07-18 |
| 6091149 | Dissolvable dielectric method and structure | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, Mark W. Michael, William S. Brennan | 2000-07-18 |
| 6091105 | Method of making a self-aligned dopant enhanced RTA MOSFET | Mark I. Gardner | 2000-07-18 |
| 6090703 | Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, William S. Brennan, Fred N. Hause, Robert Dawson, Mark W. Michael | 2000-07-18 |
| 6087705 | Trench isolation structure partially bound between a pair of low K dielectric structures | Mark I. Gardner, Charles E. May | 2000-07-11 |
| 6087706 | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-07-11 |
| 6087238 | Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof | Mark I. Gardner | 2000-07-11 |
| 6083846 | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon | Mark I. Gardner, Fred N. Hause | 2000-07-04 |
| 6080629 | Ion implantation into a gate electrode layer using an implant profile displacement layer | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-06-27 |
| 6078078 | V-gate transistor | Mark I. Gardner, Charles E. May | 2000-06-20 |
| 6077749 | Method of making dual channel gate oxide thickness for MOSFET transistor design | Mark I. Gardner, Charles E. May | 2000-06-20 |
| 6074906 | Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers | Jon D. Cheek, Derick J. Wristers | 2000-06-13 |
| 6072192 | Test structure responsive to electrical signals for determining lithographic misalignment of vias relative to electrically active elements | Mark I. Gardner, Fred N. Hause | 2000-06-06 |
| 6066885 | Subtrench conductor formed with large tilt angle implant | Robert Dawson | 2000-05-23 |
| 6064102 | Semiconductor device having gate electrodes with different gate insulators and fabrication thereof | Mark I. Gardner, Thomas E. Spikes, Jr. | 2000-05-16 |
| 6060369 | Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET | Mark I. Gardner, Derick J. Wristers | 2000-05-09 |
| 6060345 | Method of making NMOS and PMOS devices with reduced masking steps | Frederick N. Hause, Robert Dawson, Mark I. Gardner, Mark W. Michael, Bradley T. Moore +1 more | 2000-05-09 |