Issued Patents All Time
Showing 176–200 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6162687 | Method of manufacturing semiconductor device having oxide-nitride gate insulating layer | Mark I. Gardner, Charles E. May | 2000-12-19 |
| 6159804 | Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length | Mark I. Gardner, Charles E. May | 2000-12-12 |
| 6157081 | High-reliability damascene interconnect formation for semiconductor fabrication | Homi E. Nariman | 2000-12-05 |
| 6153833 | Integrated circuit having interconnect lines separated by a dielectric having a capping layer | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, Fred N. Hause, William S. Brennan | 2000-11-28 |
| 6150708 | Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density | Mark I. Gardner, Charles E. May | 2000-11-21 |
| 6150721 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-11-21 |
| 6146952 | Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof | Homi E. Nariman, Charles E. May | 2000-11-14 |
| 6146934 | Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof | Mark I. Gardner, Jack Lee | 2000-11-14 |
| 6146978 | Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance | Mark W. Michael, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2000-11-14 |
| 6144071 | Ultrathin silicon nitride containing sidewall spacers for improved transistor performance | Mark I. Gardner, Charles E. May | 2000-11-07 |
| 6140691 | Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate | Mark I. Gardner, Charles E. May | 2000-10-31 |
| 6136616 | Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength | Anthony J. Toprac, Randy Blair | 2000-10-24 |
| 6127719 | Subfield conductive layer and method of manufacture | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6127264 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 2000-10-03 |
| 6124188 | Semiconductor device and fabrication method using a germanium sacrificial gate electrode plug | Mark I. Gardner | 2000-09-26 |
| 6124197 | Adjusting the size of conductive lines based upon contact size | — | 2000-09-26 |
| 6121631 | Test structure to determine the effect of LDD length upon transistor performance | Mark I. Gardner, Fred N. Hause | 2000-09-19 |
| 6121099 | Selective spacer formation for optimized silicon area reduction | Mark I. Gardner | 2000-09-19 |
| 6118137 | Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias | Mark I. Gardner, Fred N. Hause | 2000-09-12 |
| 6117760 | Method of making a high density interconnect formation | Mark I. Gardner, Fred N. Hause | 2000-09-12 |
| 6114211 | Semiconductor device with vertical halo region and methods of manufacture | Jon D. Cheek, Derick J. Wristers, James F. Buller | 2000-09-05 |
| 6111260 | Method and apparatus for in situ anneal during ion implant | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-29 |
| 6107130 | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions | Mark I. Gardner, Derick J. Wristers | 2000-08-22 |
| 6107150 | Method of making high performance transistors using channel modulated implant for ultra thin oxide formation | Mark I. Gardner | 2000-08-22 |
| 6107129 | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance | Mark I. Gardner, Fred N. Hause | 2000-08-22 |