Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
HF

H. Jim Fulford

AMAMD: 260 patents #3 of 9,279Top 1%
TLTokyo Electron Limited: 95 patents #9 of 5,567Top 1%
Micron: 2 patents #3,728 of 6,345Top 60%
Marianna, FL: #1 of 21 inventorsTop 5%
Florida: #10 of 67,251 inventorsTop 1%
Overall (All Time): #830 of 4,157,543Top 1%
359 Patents All Time

Issued Patents All Time

Showing 151–175 of 359 patents

Patent #TitleCo-InventorsDate
6222240 Salicide and gate dielectric formed from a single layer of refractory metal Mark I. Gardner 2001-04-24
6222230 Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation Mark I. Gardner, Charles E. May 2001-04-24
6218720 Semiconductor topography employing a nitrogenated shallow trench isolation structure Mark I. Gardner, Dim-Lee Kwong 2001-04-17
6211000 Method of making high performance mosfets having high conductivity gate conductors Thomas E. Spikes, Jr., Mark I. Gardner 2001-04-03
6208015 Interlevel dielectric with air gaps to lessen capacitive coupling Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan 2001-03-27
6207995 High K integration of gate dielectric with integrated spacer formation for high speed CMOS Mark I. Gardner, Dim-Lee Kwong 2001-03-27
6207520 Rapid thermal anneal with a gaseous dopant species for formation of lightly doped regions Mark I. Gardner 2001-03-27
6204153 Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device Mark I. Gardner, Charles E. May 2001-03-20
6204148 Method of making a semiconductor device having a grown polysilicon layer Mark I. Gardner, Derick J. Wristers 2001-03-20
6201278 Trench transistor with insulative spacers Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more 2001-03-13
6200865 Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate Mark I. Gardner 2001-03-13
6197645 Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls Mark W. Michael, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more 2001-03-06
6195873 Method for decreasing contact resistance 2001-03-06
6188114 Method of forming an insulated-gate field-effect transistor with metal spacers Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more 2001-02-13
6188110 Integration of isolation with epitaxial growth regions for enhanced device formation Mark I. Gardner 2001-02-13
6188106 MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties Mark I. Gardner, Charles E. May 2001-02-13
6187620 Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions Mark I. Gardner, Derick J. Wristers 2001-02-13
6184566 Method and structure for isolating semiconductor devices after transistor formation Mark I. Gardner, Fred N. Hause 2001-02-06
6180987 Integrated circuit transistor with low-resistivity source/drain structures at least partially recessed within a dielectric base layer Mark I. Gardner 2001-01-30
6180475 Transistor formation with local interconnect overetch immunity Jon D. Cheek, Derick J. Wristers 2001-01-30
6177687 Semiconductor device having gate electrode shared between two sets of active regions and fabrication thereof Mark I. Gardner 2001-01-23
6169006 Semiconductor device having grown oxide spacers and method of manufacture thereof Mark I. Gardner, Charles E. May 2001-01-02
6168958 Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor Mark I. Gardner, Charles E. May 2001-01-02
6166354 System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication Frederick N. Hause, Robert Dawson, Mark I. Gardner, Mark W. Michael, Bradley T. Moore +1 more 2000-12-26
6162688 Method of fabricating a transistor with a dielectric underlayer and device incorporating same Mark I. Gardner, Derick J. Wristers 2000-12-19