Issued Patents All Time
Showing 251–275 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5981363 | Method and apparatus for high performance transistor devices | Mark I. Gardner, Charles E. May | 1999-11-09 |
| 5977602 | Semiconductor device having an oxygen-rich punchthrough region extending through the length of the active region | Mark I. Gardner | 1999-11-02 |
| 5976956 | Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device | Mark I. Gardner, Derick J. Wristers, Robert Dawson, Frederick N. Hause, Mark W. Michael +1 more | 1999-11-02 |
| 5976924 | Method of making a self-aligned disposable gate electrode for advanced CMOS design | Mark I. Gardner, Derick J. Wristers | 1999-11-02 |
| 5970354 | Poly recessed fabrication method for defining high performance MOSFETS | Fred N. Hause, Mark I. Gardner | 1999-10-19 |
| 5970347 | High performance mosfet transistor fabrication technique | Mark I. Gardner | 1999-10-19 |
| 5969407 | MOSFET device with an amorphized source | Mark I. Gardner, Derick J. Wristers | 1999-10-19 |
| 5968843 | Method of planarizing a semiconductor topography using multiple polish pads | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1999-10-19 |
| 5962894 | Trench transistor with metal spacers | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-10-05 |
| 5959333 | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor | Mark I. Gardner, Derick J. Wristers | 1999-09-28 |
| 5956591 | Method of making NMOS and PMOS devices having LDD structures using separate drive-in steps | — | 1999-09-21 |
| 5953626 | Dissolvable dielectric method | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, Mark W. Michael, William S. Brennan | 1999-09-14 |
| 5950091 | Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material | Mark I. Gardner, Derick J. Wristers | 1999-09-07 |
| 5946579 | Stacked mask integration technique for advanced CMOS transistor formation | Mark I. Gardner, Fred N. Hause | 1999-08-31 |
| 5943585 | Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen | Charles E. May, Mark I. Gardner | 1999-08-24 |
| 5943550 | Method of processing a semiconductor wafer for controlling drive current | Derick J. Wristers | 1999-08-24 |
| 5936287 | Nitrogenated gate structure for improved transistor performance and method for making same | Mark I. Gardner | 1999-08-10 |
| 5937299 | Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls | Mark W. Michael, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 1999-08-10 |
| 5937303 | High dielectric constant gate dielectric integrated with nitrogenated gate electrode | Mark I. Gardner | 1999-08-10 |
| 5930642 | Transistor with buried insulative layer beneath the channel region | Bradley T. Moore, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 1999-07-27 |
| 5930620 | Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures | Derrick J. Wristers, Mark I. Gardner | 1999-07-27 |
| 5930634 | Method of making an IGFET with a multilevel gate | Frederick N. Hause, Robert Dawson, Mark I. Gardner, Mark W. Michael, Bradley T. Moore +1 more | 1999-07-27 |
| 5926713 | Method for achieving global planarization by forming minimum mesas in large field areas | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, Mark W. Michael, William S. Brennan | 1999-07-20 |
| 5926714 | Detached drain MOSFET | Mark I. Gardner | 1999-07-20 |
| 5926717 | Method of making an integrated circuit with oxidizable trench liner | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, Fred N. Hause, William S. Brennan | 1999-07-20 |