Issued Patents All Time
Showing 276–300 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5924008 | Integrated circuit having local interconnect for reducing signal cross coupled noise | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, Fred N. Hause, William S. Brennan | 1999-07-13 |
| 5923983 | Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects | Mark I. Gardner, Derick J. Wristers | 1999-07-13 |
| 5923980 | Trench transistor with localized source/drain regions implanted through voids in trench | Mark I. Gardner, Frederick N. Hause | 1999-07-13 |
| 5920103 | Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection | Mark I. Gardner | 1999-07-06 |
| 5918134 | Method of reducing transistor channel length with oxidation inhibiting spacers | Mark I. Gardner, Fred N. Hause | 1999-06-29 |
| 5918130 | Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor | Fred N. Hause, Mark I. Gardner | 1999-06-29 |
| 5918129 | Method of channel doping using diffusion from implanted polysilicon | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-06-29 |
| 5918126 | Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-06-29 |
| 5916715 | Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements | Mark I. Gardner, Fred N. Hause | 1999-06-29 |
| 5915195 | Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure | Charles E. May | 1999-06-22 |
| 5908315 | Method for forming a test structure to determine the effect of LDD length upon transistor performance | Mark I. Gardner, Fred N. Hause | 1999-06-01 |
| 5904517 | Ultra thin high K spacer material for use in transistor fabrication | Mark I. Gardner, Derrick J. Wristers | 1999-05-18 |
| 5900666 | Ultra-short transistor fabrication scheme for enhanced reliability | Mark I. Gardner | 1999-05-04 |
| 5899732 | Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device | Mark I. Gardner, Derick J. Wristers, Robert Dawson, Frederick N. Hause, Mark W. Michael +1 more | 1999-05-04 |
| 5899727 | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, Mark W. Michael, William S. Brennan | 1999-05-04 |
| 5898202 | Selective spacer formation for optimized silicon area reduction | Mark I. Gardner | 1999-04-27 |
| 5895955 | MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch | Mark I. Gardner, Fred N. Hause | 1999-04-20 |
| 5894168 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 1999-04-13 |
| 5891787 | Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure | Mark I. Gardner, Derick J. Wristers | 1999-04-06 |
| 5888880 | Trench transistor with localized source/drain regions implanted through selectively grown oxide layer | Mark I. Gardner, Frederick N. Hause | 1999-03-30 |
| 5888675 | Reticle that compensates for radiation-induced lens error in a photolithographic system | Bradley T. Moore, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 1999-03-30 |
| 5885877 | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Daniel Kadosh, Mark W. Michael +2 more | 1999-03-23 |
| 5885861 | Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor | Mark I. Gardner, Derrick J. Wristers | 1999-03-23 |
| 5882983 | Trench isolation structure partially bound between a pair of low K dielectric structures | Mark I. Gardner, Charles E. May | 1999-03-16 |
| 5882974 | High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel | Mark I. Gardner | 1999-03-16 |