Issued Patents All Time
Showing 301–325 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5877050 | Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals | Mark I. Gardner, Derick J. Wristers | 1999-03-02 |
| 5877058 | Method of forming an insulated-gate field-effect transistor with metal spacers | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-03-02 |
| 5874343 | CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof | Mark I. Gardner, Derick J. Wristers | 1999-02-23 |
| 5874340 | Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls | Mark I. Gardner, Derick J. Wristers | 1999-02-23 |
| 5872049 | Nitrogenated gate structure for improved transistor performance and method for making same | Mark I. Gardner | 1999-02-16 |
| 5869879 | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions | Mark I. Gardner, Derick J. Wristers | 1999-02-09 |
| 5869866 | Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions | Mark I. Gardner, Derick J. Wristers | 1999-02-09 |
| 5854515 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-12-29 |
| 5854121 | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure | Mark I. Gardner, Derick J. Wristers | 1998-12-29 |
| 5851913 | Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process | William S. Brennan, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-12-22 |
| 5851893 | Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection | Mark I. Gardner | 1998-12-22 |
| 5851891 | IGFET method of forming with silicide contact on ultra-thin gate | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-12-22 |
| 5849621 | Method and structure for isolating semiconductor devices after transistor formation | Mark I. Gardner, Fred N. Hause | 1998-12-15 |
| 5850105 | Substantially planar semiconductor topography using dielectrics and chemical mechanical polish | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, Fred N. Hause, William S. Brennan | 1998-12-15 |
| 5847428 | Integrated circuit gate conductor which uses layered spacers to produce a graded junction | Mark I. Gardner, Derick J. Wristers | 1998-12-08 |
| 5847462 | Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, William S. Brennan, Fred N. Hause, Robert Dawson, Mark W. Michael | 1998-12-08 |
| 5846876 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-12-08 |
| 5844276 | CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof | Mark I. Gardner, Derick J. Wristers | 1998-12-01 |
| 5840451 | Individually controllable radiation sources for providing an image pattern in a photolithographic system | Bradley T. Moore, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 1998-11-24 |
| 5837557 | Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-11-17 |
| 5837572 | CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein | Mark I. Gardner, Fred N. Hause | 1998-11-17 |
| 5831306 | Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region | Mark I. Gardner, Derick J. Wristers | 1998-11-03 |
| 5830773 | Method for forming semiconductor field region dielectrics having globally planarized upper surfaces | William S. Brennan, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-11-03 |
| 5827761 | Method of making NMOS and devices with sequentially formed gates having different gate lengths | Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-10-27 |
| 5827776 | Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines | Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-10-27 |