Issued Patents All Time
Showing 326–350 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5814555 | Interlevel dielectric with air gaps to lessen capacitive coupling | Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-09-29 |
| 5811222 | Method of selectively exposing a material using a photosensitive layer and multiple image patterns | Mark I. Gardner, Derick J. Wristers | 1998-09-22 |
| 5804497 | Selectively doped channel region for increased I.sub.Dsat and method for making same | Mark I. Gardner, Fred N. Hause | 1998-09-08 |
| 5805013 | Non-volatile memory device having a floating gate with enhanced charge retention | Said Ghneim | 1998-09-08 |
| 5801075 | Method of forming trench transistor with metal spacers | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-09-01 |
| 5801088 | Method of forming a gate electrode for an IGFET | Mark I. Gardner, Derick J. Wristers | 1998-09-01 |
| 5801076 | Method of making non-volatile memory device having a floating gate with enhanced charge retention | Said Ghneim | 1998-09-01 |
| 5795809 | Semiconductor wafer fabrication process including gettering utilizing a combined oxidation technique | Mark I. Gardner, Said Ghneim | 1998-08-18 |
| 5796143 | Trench transistor in combination with trench array | Mark I. Gardner, Derick J. Wristers | 1998-08-18 |
| 5793089 | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon | Mark I. Gardner, Fred N. Hause | 1998-08-11 |
| 5793090 | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance | Mark I. Gardner, Fred N. Hause | 1998-08-11 |
| 5792706 | Interlevel dielectric with air gaps to reduce permitivity | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 1998-08-11 |
| 5789780 | Transistor with source and drain regions within the semiconductor substrate detached or laterally displaced from the transistor gate | Mark I. Gardner | 1998-08-04 |
| 5789300 | Method of making IGFETs in densely and sparsely populated areas of a substrate | — | 1998-08-04 |
| 5786256 | Method of reducing MOS transistor gate beyond photolithographically patterned dimension | Mark I. Gardner, Fred N. Hause | 1998-07-28 |
| 5783864 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Robert Dawson, Mark W. Michael, William S. Brennan, Basab Bandyopadhyay, Fred N. Hause | 1998-07-21 |
| 5783481 | Semiconductor interlevel dielectric having a polymide for producing air gaps | William S. Brennan, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-07-21 |
| 5770485 | MOSFET device with an amorphized source and fabrication method thereof | Mark I. Gardner, Derick J. Wristers | 1998-06-23 |
| 5770493 | Method of making NMOS and PMOS devices with simultaneously formed gates having different gate lengths | — | 1998-06-23 |
| 5766969 | Multiple spacer formation/removal technique for forming a graded junction | Mark I. Gardner, Derick J. Wristers | 1998-06-16 |
| 5766803 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 1998-06-16 |
| 5767012 | Method of forming a recessed interconnect structure | Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan | 1998-06-16 |
| 5767000 | Method of manufacturing subfield conductive layer | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1998-06-16 |
| 5759913 | Method of formation of an air gap within a semiconductor dielectric by solvent desorption | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 1998-06-02 |
| 5733798 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 1998-03-31 |