Issued Patents 2024
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12159839 | Semiconductor packages | Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang +1 more | 2024-12-03 |
| 12087718 | Bump structure having a side recess and semiconductor structure including the same | Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen | 2024-09-10 |
| 12087597 | Semiconductor structure comprising various via structures | Jen-Fu Liu, Ming Hung Tseng, Li-Ko Yeh, Hui-Chun Chiang, Cheng-Chieh Wu | 2024-09-10 |
| 12087563 | Semiconductor processing tool and methods of operation | Yu-Kang Huang, Yu Chuan Tai | 2024-09-10 |
| 12074024 | Semiconductor devices and methods of manufacturing thereof | Chung-Lei Chen, Anhao Cheng, Meng-I Kang | 2024-08-27 |
| 12068246 | Redistribution layer layouts on integrated circuits and methods for manufacturing the same | Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng | 2024-08-20 |
| 12040283 | Method of fabricating semiconductor structure | Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo +4 more | 2024-07-16 |
| 12021054 | Redistribution layer (RDL) layouts for integrated circuits | Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng | 2024-06-25 |
| 12009323 | Semiconductor structure | Chia-Yu Wei, Cheng-Yuan Li, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen | 2024-06-11 |
| 11973050 | Method for forming an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance | Tzu-Yu Lin, Yao-Wen Chang, Chia-Wen Zhong | 2024-04-30 |
| 11942433 | Integrated circuit package and method | Chen-Hua Yu, Jen-Fu Liu, Ming Hung Tseng, Tsung-Hsien Chiang, Tzu-Sung Huang | 2024-03-26 |
| 11935804 | Integrated circuit package and method | Tzu-Sung Huang, Ming Hung Tseng, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu +2 more | 2024-03-19 |