Issued Patents 2023
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854959 | Metal-insulator-metal device with improved performance | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Kuan-Hua Lin | 2023-12-26 |
| 11837595 | Semiconductor device structure and method for manufacturing the same | Cheng-Ying Ho, Wen-De Wang, Dun-Nian Yaung | 2023-12-05 |
| 11817470 | Stacked substrate structure with inter-tier interconnection | Jeng-Shyan Lin, Dun-Nian Yaung, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen | 2023-11-14 |
| 11798916 | 3DIC interconnect apparatus and method | Shu-Ting Tsai, Dun-Nian Yaung, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen | 2023-10-24 |
| 11791332 | Stacked semiconductor device and method | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin | 2023-10-17 |
| 11791361 | Image sensor with overlap of backside trench isolation structure and vertical transfer gate | Feng-Chi Hung, Dun-Nian Yaung, Wei Chuang Wu, Yen-Yu Chen, Chih-Kuan Yu | 2023-10-17 |
| 11791357 | Composite BSI structure and method of manufacturing the same | Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jhy-Jyi Sze, Keng-Yu Chou +3 more | 2023-10-17 |
| 11769791 | High capacitance MIM device with self aligned spacer | Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su +2 more | 2023-09-26 |
| 11764129 | Method of forming shield structure for backside through substrate vias (TSVS) | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Wei-Tao Tsai | 2023-09-19 |
| 11756936 | Backside contact to improve thermal dissipation away from semiconductor devices | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Yi-Shin Chu, Ping-Tzu Chen +1 more | 2023-09-12 |
| 11756920 | Semiconductor structure and manufacturing method thereof | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Zheng-Xun Li | 2023-09-12 |
| 11756862 | Oversized via as through-substrate-via (TSV) stop layer | Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Yi-Shin Chu, Ping-Tzu Chen | 2023-09-12 |
| 11705474 | Metal reflector grounding for noise reduction in light detector | Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Jhy-Jyi Sze, Shyh-Fann Ting +1 more | 2023-07-18 |
| 11705449 | Through silicon via design for stacking integrated circuits | Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan +2 more | 2023-07-18 |
| 11646308 | Through silicon via design for stacking integrated circuits | Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan +2 more | 2023-05-09 |
| 11600653 | Methods and apparatus for via last through-vias | Szu-Ying Chen, Pao-Tung Chen, Dun-Nian Yaung | 2023-03-07 |
| 11596800 | Interconnect structure and method of forming same | Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Feng-Chi Hung | 2023-03-07 |