Issued Patents 2023
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11855091 | Boundary design for high-voltage integration on HKMG technology | Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Ming Chyi Liu, Shih-Chung Hsiao +1 more | 2023-12-26 |
| 11823959 | FUSI gated device formation | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky +1 more | 2023-11-21 |
| 11810973 | Semiconductor structure and method of forming thereof | Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu | 2023-11-07 |
| 11799007 | Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device | Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan | 2023-10-24 |
| 11710712 | Semiconductor device and manufacturing method of the same | Jhu-Min Song, Fu-Jier Fan, Alexander Kalnitsky, Hsiao-Chin Tuan | 2023-07-25 |
| 11705449 | Through silicon via design for stacking integrated circuits | Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu +2 more | 2023-07-18 |
| 11677022 | Semiconductor structure and method of forming thereof | Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu, Huan-Chih Yuan, Jhu-Min Song | 2023-06-13 |
| 11646308 | Through silicon via design for stacking integrated circuits | Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu +2 more | 2023-05-09 |
| 11626398 | Semiconductor structure and method for manufacturing thereof | Ta-Wei Lin, Fu-Hsiung Yang, CHING-HSUN HSU, Yu-Lun Lu, Li-Hsuan Yeh +1 more | 2023-04-11 |
| 11569363 | Dishing prevention dummy structures for semiconductor devices | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Yi-Sheng Chen +1 more | 2023-01-31 |