Issued Patents 2020
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879120 | Self aligned via and method for fabricating the same | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +4 more | 2020-12-29 |
| 10867840 | Method of forming a semiconductor device | Yi-Nien Su, Shu-Huei Suen, Jyu-Horng Shieh | 2020-12-15 |
| 10866505 | Mask process correction | Hsu-Ting Huang | 2020-12-15 |
| 10867112 | Methods of making mask using transmission cross coefficient (TCC) matrix of lithography process optical system | Hsu-Ting Huang, Shinn-Sheng Yu | 2020-12-15 |
| 10866525 | Method of manufacturing a semiconductor device and apparatus for manufacturing the semiconductor device | Shinn-Sheng Yu, Hsu-Ting Huang, Kenji Yamazoe, Minfeng Chen, Shuo-Yen Chou +1 more | 2020-12-15 |
| 10866506 | Photo mask data correction method | Fu An Tien, Hsu-Ting Huang | 2020-12-15 |
| 10867833 | Buried metal for FinFET device and method | Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Chih-Ming Lai, Charles Chew-Yuen Young | 2020-12-15 |
| 10861698 | Pattern fidelity enhancement | Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen +3 more | 2020-12-08 |
| 10861790 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng +6 more | 2020-12-08 |
| 10860774 | Methodology for pattern density optimization | Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu +3 more | 2020-12-08 |
| 10847460 | Advanced metal connection with metal cut | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +6 more | 2020-11-24 |
| 10833061 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun Li Chen +3 more | 2020-11-10 |
| 10818509 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2020-10-27 |
| 10817635 | Multiple patterning method for semiconductor devices | Ken-Hsien Hsieh, Chih-Ming Lai, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wang | 2020-10-27 |
| 10796055 | Method for coloring circuit layout and system for performing the same | Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang +5 more | 2020-10-06 |
| 10790155 | Method of manufacturing semiconductor devices | Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen, Ken-Hsien Hsieh, Chin-Hsiang Lin | 2020-09-29 |
| 10784168 | Dummy MOL removal for performance enhancement | Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +4 more | 2020-09-22 |
| 10770303 | Mechanisms for forming patterns using multiple lithography processes | Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau | 2020-09-08 |
| 10770304 | Hybrid double patterning method for semiconductor manufacture | Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai | 2020-09-08 |
| 10763365 | Metal rail conductors for non-planar semiconductor devices | Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +5 more | 2020-09-01 |
| 10763113 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh | 2020-09-01 |
| 10747938 | Method for integrated circuit manufacturing | Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang +5 more | 2020-08-18 |
| 10748767 | Method for forming conductive lines | Yung-Sung Yen, Ken-Hsien Hsieh | 2020-08-18 |
| 10734321 | Integrated circuit and method of manufacturing same | Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang +6 more | 2020-08-04 |
| 10727113 | Methods of forming metal layer structures in semiconductor devices | Ethan Hsiao, Chien-Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang +1 more | 2020-07-28 |