Issued Patents 2020
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10868239 | Gradient protection layer in MTJ manufacturing | Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien-Chung Huang +2 more | 2020-12-15 |
| 10867840 | Method of forming a semiconductor device | Yi-Nien Su, Shu-Huei Suen, Ru-Gun Liu | 2020-12-15 |
| 10862023 | Semiconductor structure and manufacturing method of the same | Tai-Yen Peng, Yu-Shu Chen, Chien-Chung Huang, Sin-Yi Yang, Chen-Jung Wang +2 more | 2020-12-08 |
| 10770345 | Integrated circuit and fabrication method thereof | Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang +3 more | 2020-09-08 |
| 10755945 | Metal contacts on metal gates and methods thereof | Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang +9 more | 2020-08-25 |
| 10755974 | Interconnect structure and method of forming same | Ming-Hui Chu, Chih-Yuan Ting | 2020-08-25 |
| 10734580 | Memory device and fabrication method thereof | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2020-08-04 |
| 10714383 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Chih-Yuan Ting, Minghsing Tsai | 2020-07-14 |
| 10672651 | Method for forming structure of dual damascene structures having via hole and trench | Tai-Yen Peng | 2020-06-02 |
| 10665467 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2020-05-26 |
| 10651373 | Memory device and fabrication method thereof | Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang +3 more | 2020-05-12 |
| 10651047 | Double patterning method | Chia-Ying Lee | 2020-05-12 |
| 10535556 | Integrated circuit with conductive line having line-ends | Chih-Yuan Ting, Pei-Wen Huang | 2020-01-14 |