Issued Patents 2020
Showing 101–125 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10629701 | Self-aligned gate cut method and multilayer gate-cut pillar structure | Youngtag Woo, Hui Zang | 2020-04-21 |
| 10629699 | Gate height control and ILD protection | Andrew M. Greene, John R. Sporre, Stan Tsai | 2020-04-21 |
| 10629694 | Gate contact and cross-coupling contact formation | Hui Zang, Haiting Wang, Scott Beasor | 2020-04-21 |
| 10627720 | Overlay mark structures | Lei Sun, John H. Zhang, Shao Beng Law, Guoxiang Ning, Xunyuan Zhang | 2020-04-21 |
| 10622458 | Self-aligned contact for vertical field effect transistor | Brent A. Anderson, Steven R. Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang | 2020-04-14 |
| 10622475 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Cheng Chi, Chanro Park, Tenko Yamashita | 2020-04-14 |
| 10622457 | Forming replacement low-K spacer in tight pitch fin field effect transistors | Xiuyu Cai, Chun-Chen Yeh, Qing Liu | 2020-04-14 |
| 10622357 | FinFET including tunable fin height and tunable fin width ratio | Xiuyu Cai, Qing Liu, Chun-Chen Yeh | 2020-04-14 |
| 10622260 | Vertical transistor with reduced parasitic capacitance | Chanro Park, Kangguo Cheng | 2020-04-14 |
| 10615277 | VFET CMOS dual epitaxy integration | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-04-07 |
| 10608082 | Field-effect transistors including multiple gate lengths | Julien Frougier | 2020-03-31 |
| 10607893 | Middle of line structures | Hui Zang | 2020-03-31 |
| 10600778 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-03-24 |
| 10600914 | Isolation pillar first gate structures and methods of forming same | Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren +2 more | 2020-03-24 |
| 10593757 | Integrated circuits having converted self-aligned epitaxial etch stop | Jiehui Shu, Hui Zang, Haiting Wang | 2020-03-17 |
| 10593782 | Self-aligned finFET formation | Cheng Chi, Fee Li Lie, Chi-Chun Liu | 2020-03-17 |
| 10593780 | Forming replacement low-K spacer in tight pitch fin field effect transistors | Xiuyu Cai, Chun-Chen Yeh, Qing Liu | 2020-03-17 |
| 10593593 | Methods, apparatus, and system for protecting cobalt formations from oxidation during semiconductor device formation | Vimal Kamineni, Mark V. Raymond | 2020-03-17 |
| 10586706 | Gate cut with high selectivity to preserve interlevel dielectric layer | Andrew M. Greene, Ryan O. Jung | 2020-03-10 |
| 10586736 | Hybrid fin cut with improved fin profiles | Haiting Wang, Shesh Mani Pandey, Hui Zang, Garo Derderian, Scott Beasor | 2020-03-10 |
| 10580692 | Integration of air spacer with self-aligned contact in transistor | Chanro Park, Julien Frougier, Kangguo Cheng | 2020-03-03 |
| 10573755 | Nanosheet FET with box isolation on substrate | Julien Frougier, Kangguo Cheng, Nicolas Loubet | 2020-02-25 |
| 10573753 | Oxide spacer in a contact over active gate finFET and method of production thereof | Hui Zang, Laertis Economikos, Jiehui Shu | 2020-02-25 |
| 10566248 | Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar | Daniel Chanemougame, Chanro Park, Guillaume Bouche | 2020-02-18 |
| 10566443 | Nanosheet transitor with optimized junction and cladding defectivity control | Kangguo Cheng, Nicolas Loubet, Tenko Yamashita, Chun-Chen Yeh | 2020-02-18 |