Issued Patents 2020
Showing 126–141 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10566442 | Vertical field effect transistor with reduced parasitic capacitance | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-02-18 |
| 10566438 | Nanosheet transistor with dual inner airgap spacers | Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita | 2020-02-18 |
| 10566436 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng | 2020-02-18 |
| 10566201 | Gate cut method after source/drain metallization | Chanro Park, Hui Zang, Laertis Economikos, Andre P. Labonte | 2020-02-18 |
| 10559686 | Methods of forming gate contact over active region for vertical FinFET, and structures formed thereby | Hui Zang, Steven R. Soss | 2020-02-11 |
| 10559656 | Wrap-all-around contact for nanosheet-FET and method of forming same | Emilie Bourjot, Julien Frougier, Yi Qi, Hui Zang, Hsien-Ching Lo +1 more | 2020-02-11 |
| 10553698 | Methods, apparatus and system for a self-aligned gate cut on a semiconductor device | Hui Zang, Laertis Economikos | 2020-02-04 |
| 10553705 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2020-02-04 |
| 10553486 | Field effect transistors with self-aligned metal plugs and methods | Hui Zang, Laertis Economikos | 2020-02-04 |
| 10546853 | Metal resistors integrated into poly-open-chemical-mechanical-polishing (POC) module and method of production thereof | Laertis Economikos, Hui Zang | 2020-01-28 |
| 10546945 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2020-01-28 |
| 10546942 | Nanosheet transistor with optimized junction and cladding defectivity control | Kangguo Cheng, Nicolas Loubet, Tenko Yamashita, Chun-Chen Yeh | 2020-01-28 |
| 10546856 | CMOS structure having low resistance contacts and fabrication method | Qing Liu, Xiuyu Cai, Chun-Chen Yeh | 2020-01-28 |
| 10546854 | Methods of forming V0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness | Xunyuan Zhang | 2020-01-28 |
| 10541272 | Steep-switch vertical field effect transistor | Daniel Chanemougame, Julien Frougier, Nicolas Loubet | 2020-01-21 |
| 10529826 | Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices | Julien Frougier, Chanro Park, Kangguo Cheng | 2020-01-07 |