Issued Patents 2020
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840245 | Semiconductor device with reduced parasitic capacitance | Jiehui Shu, Haiting Wang | 2020-11-17 |
| 10825910 | Shaped gate caps in dielectric-lined openings | Hui Zang | 2020-11-03 |
| 10741451 | FinFET having insulating layers between gate and source/drain contacts | Hui Zang, Laertis Economikos, Chanro Park, Ruilong Xie | 2020-08-11 |
| 10741656 | Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same | Hui Zang, Ruilong Xie, Laertis Economikos | 2020-08-11 |
| 10727133 | Method of forming gate structure with undercut region and resulting device | Qun Gao, Balaji Kannan, Haiting Wang | 2020-07-28 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven R. Soss, Lars Liebmann +1 more | 2020-06-30 |
| 10672710 | Interconnect structures with reduced capacitance | Sunil Kumar Singh | 2020-06-02 |
| 10586736 | Hybrid fin cut with improved fin profiles | Haiting Wang, Ruilong Xie, Hui Zang, Garo Derderian, Scott Beasor | 2020-03-10 |
| 10535771 | Method for forming replacement air gap | Laertis Economikos, Hui Zang, Haiting Wang, Jinping Liu | 2020-01-14 |