Issued Patents 2020
Showing 51–75 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10756203 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2020-08-25 |
| 10756096 | Integrated circuit structure with complementary field effect transistor and buried metal interconnect and method | Bipul C. Paul | 2020-08-25 |
| 10749031 | Large area contacts for small transistors | Xiuyu Cai, Qing Liu, Chun-Chen Yeh | 2020-08-18 |
| 10749038 | Width adjustment of stacked nanowires | Kangguo Cheng, Xin Miao, Tenko Yamashita | 2020-08-18 |
| 10746691 | Ion-sensitive field effect transistor (ISFET) with enhanced sensitivity | Kangguo Cheng, Chanro Park, Juntao Li | 2020-08-18 |
| 10741639 | Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection | Nicolas Loubet, Robin Hsin Kuo Chao, Julien Frougier | 2020-08-11 |
| 10741675 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2020-08-11 |
| 10741668 | Short channel and long channel devices | Bala Haran, Balaji Kannan, Katsunori Onishi, Vimal Kamineni | 2020-08-11 |
| 10741656 | Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same | Hui Zang, Shesh Mani Pandey, Laertis Economikos | 2020-08-11 |
| 10741451 | FinFET having insulating layers between gate and source/drain contacts | Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park | 2020-08-11 |
| 10734525 | Gate-all-around transistor with spacer support and methods of forming same | Julien Frougier, Christopher M. Prindle, Nigel G. Cave | 2020-08-04 |
| 10734499 | Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita | 2020-08-04 |
| 10727120 | Controlling back-end-of-line dimensions of semiconductor devices | Sean Xuan Lin, Guoxiang Ning, Lei Sun | 2020-07-28 |
| 10727308 | Gate contact structure for a transistor | Hao Tang, Cheng Chi, Daniel Chanemougame, Lars Liebmann, Mark V. Raymond | 2020-07-28 |
| 10727136 | Integrated gate contact and cross-coupling contact formation | Hui Zang, Chanro Park, Laertis Economikos | 2020-07-28 |
| 10720391 | Method of forming a buried interconnect and the resulting devices | Bipul C. Paul, Lars Liebmann | 2020-07-21 |
| 10714470 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-07-14 |
| 10714591 | Gate structure for a transistor device with a novel pillar structure positioned thereabove | Youngtag Woo, Hui Zang | 2020-07-14 |
| 10714567 | Nanosheet field-effect transistor with substrate isolation | Julien Frougier | 2020-07-14 |
| 10707206 | Gate cut isolation formed as layer against sidewall of dummy gate mandrel | Hui Zang, Laertis Economikos | 2020-07-07 |
| 10707218 | Two port SRAM cell using complementary nano-sheet/wire transistor devices | Bipul C. Paul | 2020-07-07 |
| 10699957 | Late gate cut using selective dielectric deposition | Hui Zang, Jiehui Shu, Chanro Park, Laertis Economikos | 2020-06-30 |
| 10700173 | FinFET device with a wrap-around silicide source/drain contact structure | Yi Qi, Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong +4 more | 2020-06-30 |
| 10699965 | Removal of epitaxy defects in transistors | Andrew M. Greene, Christopher M. Prindle, Pietro Montanini | 2020-06-30 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Chanro Park, Daniel Chanemougame, Steven R. Soss, Lars Liebmann, Hui Zang +1 more | 2020-06-30 |