Issued Patents 2018
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10032717 | Vertical fuse structures | Juntao Li, Chih-Chao Yang | 2018-07-24 |
| 10032769 | Cmos compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-07-24 |
| 10032711 | Integrating metal-insulator-metal capacitors with air gap process flow | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-07-24 |
| 10020254 | Integration of super via structure in BEOL | Ruqiang Bao, Joe Lee, Yann Mignot, Hosadurga Shobha, Yongan Xu | 2018-07-10 |
| 10020255 | Integration of super via structure in BEOL | Ruqiang Bao, Joe Lee, Yann Mignot, Hosadurga Shobha, Yongan Xu | 2018-07-10 |
| 10014255 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2018-07-03 |
| 10014221 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-07-03 |
| 10002962 | Vertical FET structure | Brent A. Anderson, Huiming Bu, Fee Li Lie, Edward J. Nowak | 2018-06-19 |
| 9991267 | Forming eDRAM unit cell with VFET and via capacitance | Brent A. Anderson, Huiming Bu, Xuefeng Liu | 2018-06-05 |
| 9966454 | Contact area to trench silicide resistance reduction by high-resistance interface removal | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-05-08 |
| 9966308 | Semiconductor device and method of forming the semiconductor device | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Chih-Chao Yang | 2018-05-08 |
| 9954101 | Precise junction placement in vertical semiconductor devices using etch stop layers | Huiming Bu, Liying Jiang, Siyuranga O. Koswatta | 2018-04-24 |
| 9954107 | Strained FinFET source drain isolation | Kangguo Cheng, Veeraraghavan S. Basker, Theodorus E. Standaert | 2018-04-24 |
| 9954058 | Self-aligned air gap spacer for nanosheet CMOS devices | Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin | 2018-04-24 |
| 9947663 | FinFET CMOS with silicon fin N-channel FET and silicon germanium fin P-channel FET | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-04-17 |
| 9947791 | FinFET with merge-free fins | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeg Yin | 2018-04-17 |
| 9947593 | Extra gate device for nanosheet | Bruce B. Doris, Terence B. Hook | 2018-04-17 |
| 9941378 | Air-gap top spacer and self-aligned metal gate for vertical FETs | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-04-10 |
| 9941392 | Gate planarity for FinFET using dummy polish stop | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-04-10 |
| 9929091 | Vertical fuse structures | Juntao Li, Chih-Chao Yang | 2018-03-27 |
| 9917082 | Approach to fabrication of an on-chip resistor with a field effect transistor | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-03-13 |
| 9917105 | Replacement fin process in SSOI wafer | Bruce B. Doris, Hong He, Ali Khakifirooz | 2018-03-13 |
| 9917081 | Semiconductor device including finFET and fin varactor | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-03-13 |
| 9911657 | Semiconductor device including finFET and fin varactor | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-03-06 |
| 9911738 | Vertical-transport field-effect transistors with a damascene gate strap | Hiroaki Niimi, Kwan-Yong Lim, Brent A. Anderson | 2018-03-06 |