Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
JW

Junli Wang

IBM: 58 patents #27 of 10,623Top 1%
Globalfoundries: 6 patents #51 of 961Top 6%
SSStmicroelectronics Sa: 3 patents #16 of 127Top 15%
Slingerlands, NY: #1 of 32 inventorsTop 4%
New York: #16 of 11,825 inventorsTop 1%
Overall (2018): #127 of 503,207Top 1%
61 Patents 2018

Issued Patents 2018

Showing 51–61 of 61 patents

Patent #TitleCo-InventorsDate
9911663 Preventing buried oxide gouging during planar and FinFET processing on SOI Kern Rim 2018-03-06
9911601 Epitaxial silicon germanium fin formation using sacrificial silicon fin templates Hong He, Juntao Li, Chih-Chao Yang 2018-03-06
9905469 Method and structure for forming FinFET CMOS with dual doped STI regions Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2018-02-27
9893154 Recess liner for silicon germanium fin formation Timothy J. McArdle, Judson R. Holt 2018-02-13
9881869 Middle of the line integrated efuse in trench EPI structure Hong He, Juntao Li, Chih-Chao Yang 2018-01-30
9882048 Gate cut on a vertical field effect transistor with a defined-width inorganic mask Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre 2018-01-30
9882006 Silicon germanium fin channel formation Hong He, Nicolas Loubet 2018-01-30
9881926 Static random access memory (SRAM) density scaling by using middle of line (MOL) flow Veeraraghavan S. Basker, Kangguo Cheng, Sivananda K. Kanakasabapathy, Theodorus E. Standaert 2018-01-30
9876009 CMOS compatible fuse or resistor using self-aligned contacts Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2018-01-23
9871116 Replacement metal gate structures Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2018-01-16
9865739 Replacement metal gate structures Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2018-01-09