Issued Patents 2017
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852994 | Embedded vialess bridges | — | 2017-12-26 |
| 9847277 | Staged via formation from both sides of chip | Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Piyush Savalia | 2017-12-19 |
| 9837344 | Low CTE interposer | Kishor Desai | 2017-12-05 |
| 9832887 | Micro mechanical anchor for 3D architecture | Liang Wang, Ilyas Mohammed | 2017-11-28 |
| 9818723 | Multi-chip package with interconnects extending through logic chip | — | 2017-11-14 |
| 9812433 | Batch process fabrication of package-on-package microelectronic assemblies | Ilyas Mohammed, Liang Wang | 2017-11-07 |
| 9806017 | Flip-chip, face-up and face-down centerbond memory wirebond assemblies | Richard Dewitt Crisp, Wael Zohni | 2017-10-31 |
| 9773723 | SSI PoP | — | 2017-09-26 |
| 9761517 | Porous alumina templates for electronic packages | Rajesh Katkar, Cyprian Emeka Uzoh, Ilyas Mohammed | 2017-09-12 |
| 9754866 | Reversed build-up substrate for 2.5D | Liang Wang, Rajesh Katkar, Hong Shen, Cyprian Emeka Uzoh | 2017-09-05 |
| 9735093 | Stacked chip-on-board module with edge connector | Wael Zohni | 2017-08-15 |
| 9728495 | Reconfigurable PoP | Richard Dewitt Crisp, Wael Zohni | 2017-08-08 |
| 9716075 | Semiconductor chip assembly and method for making same | Teck-Gyu Kang, Wei-Shun Wang, Hiroaki Sato, Kiyoaki Hashimoto, Yoshikuni Nakadaira +3 more | 2017-07-25 |
| 9711401 | Reliable packaging and interconnect structures | Cyprian Emeka Uzoh, Craig Mitchell | 2017-07-18 |
| 9691731 | Package-on-package assembly with wire bonds to encapsulation surface | Hiroaki Sato, Teck-Gyu Kang, Philip R. Osborn, Wei-Shun Wang, Ellis Chau +6 more | 2017-06-27 |
| 9685401 | Structures for heat dissipating interposers | Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Charles G. Woychik +1 more | 2017-06-20 |
| 9679613 | TFD I/O partition for high-speed, high-density applications | Zhuowen Sun, Kyong-Mo Bang, Wael Zohni | 2017-06-13 |
| 9679876 | Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2017-06-13 |
| 9679838 | Stub minimization for assemblies without wirebonds to package substrate | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2017-06-13 |
| 9666560 | Multi-chip microelectronic assembly with built-up fine-patterned circuit structure | Liang Wang, Guilian Gao, Hong Shen, Rajesh Katkar | 2017-05-30 |
| 9666450 | Substrate and assembly thereof with dielectric removal for increased post height | Kazuo Sakuma, Philip Damberg | 2017-05-30 |
| 9659812 | Microelectronic elements with post-assembly planarization | Vage Oganesian, Craig Mitchell, Ilyas Mohammed, Piyush Savalia | 2017-05-23 |
| 9659858 | Low-stress vias | Ilyas Mohammed, Cyprian Emeka Uzoh | 2017-05-23 |
| 9640515 | Multiple die stacking for two or more die | Wael Zohni | 2017-05-02 |
| 9640437 | Methods of forming semiconductor elements using micro-abrasive particle stream | Vage Oganesian, Craig Mitchell, Ilyas Mohammed, Piyush Savalia | 2017-05-02 |