Issued Patents 2016
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529959 | System and method for pattern correction in e-beam lithography | Hung-Chun Wang, Hsu-Ting Huang, Wen-Chun Huang | 2016-12-27 |
| 9530660 | Multiple directed self-assembly patterning process | Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, Kuan-Hsin Lo, Tsai-Sheng Gau +1 more | 2016-12-27 |
| 9524939 | Multiple edge enabled patterning | Ming-Feng Shieh, Ya Hui Chang, Tsong-Hua Ou, Ken-Hsien Hsieh, Burn Jeng Lin | 2016-12-20 |
| 9502261 | Spacer etching process for integrated circuit design | Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh +6 more | 2016-11-22 |
| 9495507 | Method for integrated circuit mask patterning | Jue-Chin Yu, Lun Hsieh, Pi-Tsung Chen, Shuo-Yen Chou | 2016-11-15 |
| 9478540 | Adaptive fin design for FinFETs | Tsong-Hua Ou, Shu-Min Chen, Pin-Dai Sue, Li-Chun Tien | 2016-10-25 |
| 9478636 | Method of forming semiconductor device including source/drain contact having height below gate stack | Chih-Liang Chen, Chih-Ming Lai, Kam-Tou Sio, Meng-Hung Shen, Chun-Hung Liou +2 more | 2016-10-25 |
| 9472501 | Conductive line patterning | Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting | 2016-10-18 |
| 9466486 | Method for integrated circuit patterning | Ming-Feng Shieh, Hung-Chang Hsieh, Tien-I Bao, Chung-Ju Lee, Shau-Lin Shue | 2016-10-11 |
| 9448470 | Method for making a mask with a phase bar in an integrated circuit design layout | Shou-Yen Chou, Hoi-Tou Ng, Ken-Hsien Hsieh, Yi-Yin Chen | 2016-09-20 |
| 9449880 | Fin patterning methods for increased process margin | Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, Chih-Ming Lai, Huan-Just Lin +2 more | 2016-09-20 |
| 9431297 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee +4 more | 2016-08-30 |
| 9418196 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Lee-Chung Lu | 2016-08-16 |
| 9418868 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2016-08-16 |
| 9418191 | Providing electron beam proximity effect correction by simulating write operations of polygonal shapes | Hung-Chun Wang, Jeng-Horng Chen, Shy-Jay Lin, Chia-Ping Chiang, Cheng Kun Tsai +1 more | 2016-08-16 |
| 9411924 | Methodology for pattern density optimization | Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu +3 more | 2016-08-09 |
| 9412649 | Method of fabricating semiconductor device | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2016-08-09 |
| 9404743 | Method for validating measurement data | Chui-Jung Chiu, Jen-Chieh Lo, Ying-Chou Cheng | 2016-08-02 |
| 9395618 | Enhanced EUV lithography system | Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang | 2016-07-19 |
| 9390217 | Methodology of optical proximity correction optimization | Hung-Chun Wang, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Feng-Ju Chang +2 more | 2016-07-12 |
| 9391056 | Mask optimization for multi-layer contacts | Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting +1 more | 2016-07-12 |
| 9390223 | Method of determining whether a layout is colorable | Wen-Li Cheng, Ming-Hui Chih, Chia-Ping Chiang, Ken-Hsien Hsieh, Tsong-Hua Ou +1 more | 2016-07-12 |
| 9362169 | Self-aligned semiconductor fabrication with fosse features | Shih-Ming Chang, Ken-Hsien Hsieh, Chih-Ming Lai, Ming-Feng Shieh, Tsai-Sheng Gau | 2016-06-07 |
| 9362132 | Systems and methods for a sequential spacer scheme | Shih-Ming Chang, Ming-Feng Shieh, Tsai-Sheng Gau | 2016-06-07 |
| 9362119 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai +1 more | 2016-06-07 |