Issued Patents 2016
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9436793 | Tier based layer promotion and demotion | Yen-Hung Lin, Chi Wei Hu, Chung-Hsing Wang, Chin-Chou Liu | 2016-09-06 |
| 9418196 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-08-16 |
| 9405880 | Semiconductor arrangement formation | Yen-Hung Lin, Chi Wei Hu, Chung-Hsing Wang, Chin-Chou Liu | 2016-08-02 |
| 9317650 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng | 2016-04-19 |
| 9292645 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-03-22 |