Issued Patents 2016
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9471742 | Method for displaying timing information of an integrated circuit floorplan in real time | Yi-Lin Chuang, Yun-Han Lee | 2016-10-18 |
| 9418196 | Layout optimization for integrated circuit design | Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-08-16 |
| 9384307 | Stitch and trim methods for double patterning compliant standard cell design | Chin-Hsiung Hsu, Chung-Hsing Wang | 2016-07-05 |
| 9380709 | Method of cutting conductive patterns | Chin-Hsiung Hsu, Tsong-Hua Ou, Wen-Hao Chen | 2016-06-28 |
| 9355202 | Promoting efficient cell usage to boost QoR in automated design | Ya Chen Wang, Tan-Li Chou | 2016-05-31 |
| 9317650 | Double patterning technology (DPT) layout routing | Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng | 2016-04-19 |
| 9292645 | Layout optimization for integrated circuit design | Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-03-22 |
| 9262577 | Layout method and system for multi-patterning integrated circuits | Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu | 2016-02-16 |