Issued Patents 2016
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9367654 | Variation modeling | Chi-Wen Chang, Hui Yu Lee, Jui-Feng Kuan, Chin-Hua Wen, Wen-Shen Chou | 2016-06-14 |
| 9361425 | Method and apparatus for modeling multi-terminal MOS device for LVS and PDK | Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih-Ming Yang | 2016-06-07 |
| 9361423 | RC corner solutions for double patterning technology | Ke-Ying Su, Hsiao-Shu Chao | 2016-06-07 |
| 9355205 | Method and apparatus of a three dimensional integrated circuit | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan | 2016-05-31 |
| 9348965 | Parasitic component library and method for efficient circuit design and simulation using the same | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Tao Wen Chung, Jui-Feng Kuan | 2016-05-24 |
| 9335624 | Multi-patterning system and method using pre-coloring or locked patterns | Hui Yu Lee, Chi-Wen Chang, Chih-Ming Yang, Ya Yun Liu | 2016-05-10 |
| 9317650 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang | 2016-04-19 |
| 9275186 | Optimization for circuit migration | Lee-Chung Lu, Chung-Hsing Wang, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2016-03-01 |
| 9262558 | RC extraction for single patterning spacer technique | Cheng-I Huang, Hsiao-Shu Chao | 2016-02-16 |
| 9230052 | Method of generating a simulation model of a predefined fabrication process | Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao | 2016-01-05 |