Issued Patents 2016
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9519735 | Method of failure analysis | Chin-Cheng Kuo, Kmin Hsu, Wei Hu, Wei Min Chan | 2016-12-13 |
| 9418200 | Integrated circuit design system and method of generating proposed device array layout | Ching-Yu Chai, Chin-Sheng Chen, Wei Hu | 2016-08-16 |
| 9411926 | Method of performing circuit simulation and generating circuit layout | Hui Yu Lee, Feng-Wei Kuo, Simon Yi-Hung Chen | 2016-08-09 |
| 9367654 | Variation modeling | Chi-Wen Chang, Hui Yu Lee, Yi-Kan Cheng, Chin-Hua Wen, Wen-Shen Chou | 2016-06-14 |
| 9355205 | Method and apparatus of a three dimensional integrated circuit | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Yi-Kan Cheng | 2016-05-31 |
| 9348965 | Parasitic component library and method for efficient circuit design and simulation using the same | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Tao Wen Chung, Yi-Kan Cheng | 2016-05-24 |