Issued Patents 2016
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9514979 | Trench formation using horn shaped spacer | Tsung-Min Huang, Yung-Hsu Wu | 2016-12-06 |
| 9502261 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh +6 more | 2016-11-22 |
| 9502249 | Masking process and structures formed thereby | Tsung-Min Huang | 2016-11-22 |
| 9490205 | Integrated circuit interconnects and methods of making same | Cheng-Hsiung Tsai, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming-Han Lee | 2016-11-08 |
| 9490163 | Tapered sidewall conductive lines and formation thereof | Chien-Hua Huang, Hsin-Chieh Yao | 2016-11-08 |
| 9484257 | Semiconductor devices and methods of manufacture thereof | Hsin-Chieh Yao, Tien-I Bao, Shau-Lin Shue | 2016-11-01 |
| 9478430 | Method of semiconductor integrated circuit fabrication | Hsin-Chieh Yao, Cheng-Hsiung Tsai, Tien-I Bao | 2016-10-25 |
| 9466486 | Method for integrated circuit patterning | Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tien-I Bao, Shau-Lin Shue | 2016-10-11 |
| 9449839 | Self-assembled monolayer for pattern formation | Tsung-Min Huang, Chien-Hua Huang | 2016-09-20 |
| 9437540 | Additional etching to increase via contact area | Pei-Yi Lin, Shau-Lin Shue | 2016-09-06 |
| 9431297 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Yung-Sung Yen +4 more | 2016-08-30 |
| 9418868 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2016-08-16 |
| 9418886 | Method of forming conductive features | Chien-Hua Huang, Chieh-Han Wu | 2016-08-16 |
| 9418862 | Method for integrated circuit patterning | Tsung-Min Huang, Chieh-Han Wu, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu | 2016-08-16 |
| 9412649 | Method of fabricating semiconductor device | Yung-Sung Yen, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2016-08-09 |
| 9412651 | Air-gap formation in interconnect structures | Cheng-Hsiung Tsai, Tien-I Bao | 2016-08-09 |
| 9406614 | Material and process for copper barrier layer | Tsung-Min Huang | 2016-08-02 |
| 9384994 | Method of forming multiple patterning spacer structures | Chih Wei Lu, Shau-Lin Shue | 2016-07-05 |
| 9373586 | Copper etching integration scheme | Chih Wei Lu, Hsiang-Huan Lee, Tien-I Bao | 2016-06-21 |
| 9368348 | Self-aligned patterning process | Tsung-Min Huang | 2016-06-14 |
| 9355865 | Semiconductor patterning | Cheng-Hsiung Tsai, Tsung-Jung Tsai, Yu-Sheng Chang | 2016-05-31 |
| 9349595 | Methods of manufacturing semiconductor devices | Cheng-Hsiung Tsai, Hsin-Chieh Yao, Tien-I Bao | 2016-05-24 |
| 9337055 | Chemical circulation system and methods of cleaning chemicals | Chien-Hua Huang | 2016-05-10 |
| 9330989 | System and method for chemical-mechanical planarization of a metal layer | Yung-Hsu Wu, Shih-Kang Fu, Hsin-Chieh Yao, Hsiang-Huan Lee, Hai-Ching Chen +1 more | 2016-05-03 |
| 9318377 | Etch damage and ESL free dual damascene metal interconnect | Sunil Kumar Singh, Tien-I Bao | 2016-04-19 |