Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
AR

Alexander Reznicek

IBM: 126 patents #3 of 10,295Top 1%
Globalfoundries: 48 patents #4 of 2,145Top 1%
IBInternational Business: 1 patents #1 of 8Top 15%
Troy, NY: #1 of 72 inventorsTop 2%
New York: #2 of 11,723 inventorsTop 1%
Overall (2016): #21 of 481,213Top 1%
175 Patents 2016

Issued Patents 2016

Showing 76–100 of 175 patents

Patent #TitleCo-InventorsDate
9425293 Stacked nanowires with multi-threshold voltage solution for pFETs Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2016-08-23
9425291 Stacked nanosheets by aspect ratio trapping Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2016-08-23
9419074 Non-planar semiconductor device with aspect ratio trapping Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz 2016-08-16
9419138 Embedded carbon-doped germanium as stressor for germanium nFET devices Jeffrey L. Dittmar, Keith E. Fogel, Sebastian Naczas, Devendra K. Sadana 2016-08-16
9419079 Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same 2016-08-16
9419078 Floating body memory with asymmetric channel Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz 2016-08-16
9418841 Type III-V and type IV semiconductor device formation Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz 2016-08-16
9412865 Reduced resistance short-channel InGaAs planar MOSFET Pranita Kerber, Qiqing C. Ouyang 2016-08-09
9406545 Bulk semiconductor fins with self-aligned shallow trench isolation structures Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz 2016-08-02
9406529 Formation of FinFET junction Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott 2016-08-02
9406748 Perfectly shaped controlled nanowires Karthik Balakrishnan, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi 2016-08-02
9406506 Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon Keith E. Fogel, Pouya Hashemi, Ali Khakifirooz 2016-08-02
9401373 Multi-fin finFETs with merged-fin source/drains and replacement gates Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz 2016-07-26
9401311 Self aligned structure and method for high-K metal gate work function tuning Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz 2016-07-26
9390925 Silicon—germanium (SiGe) fin formation Kangguo Cheng, Ali Khakifirooz, Dominic J. Schepis 2016-07-12
9391198 Strained semiconductor trampoline Pranita Kerber, Qiqing C. Ouyang, Dominic J. Schepis 2016-07-12
9391173 FinFET device with vertical silicide on recessed source/drain epitaxy regions Keith E. Fogel, Pranita Kerber, Qiqing C. Ouyang 2016-07-12
9391077 SiGe and Si FinFET structures and methods for making the same Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz 2016-07-12
9391069 MIM capacitor with enhanced capacitance formed by selective epitaxy Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Raghavasimhan Sreenivasan 2016-07-12
9390980 III-V compound and germanium compound nanowire suspension with germanium-containing release layer Guy M. Cohen, Isaac Lauer, Jeffrey W. Sleight 2016-07-12
9385218 Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy Kangguo Cheng, Pouya Hashemi 2016-07-05
9385231 Device structure with increased contact area and reduced gate capacitance Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz 2016-07-05
9385023 Method and structure to make fins with different fin heights and no topography Kangguo Cheng, Joel P. de Souza, Ali Khakifirooz, Dominic J. Schepis 2016-07-05
9378952 Tall relaxed high percentage silicon germanium fins on insulator Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki 2016-06-28
9379243 Field-effect transistor with aggressively strained fins Pouya Hashemi, Ali Khakifirooz 2016-06-28